This patch adds SIMD register variants for and, ior, xor and not - similarly to
add/sub, the H/W supports it, and it'll be more efficient if the values are
there already, e.g. if passed as [u]int64x1_t parameters.
gcc/ChangeLog:
* config/aarch64/aarch64.md (<optab><mode>3, one_cmpl<mode>2):
Add SIMD-register variant.
* config/aarch64/iterators.md (Vbtype): Add value for SI.diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 0a8ca4bcc7941f912c8d42200b33206d4188fa48..8eaf1be3ba6e39ca00a2ae3905e84375b354ccd8 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -2608,12 +2608,16 @@
;; -------------------------------------------------------------------
(define_insn "<optab><mode>3"
- [(set (match_operand:GPI 0 "register_operand" "=r,rk")
- (LOGICAL:GPI (match_operand:GPI 1 "register_operand" "%r,r")
- (match_operand:GPI 2 "aarch64_logical_operand" "r,<lconst>")))]
+ [(set (match_operand:GPI 0 "register_operand" "=r,rk,w")
+ (LOGICAL:GPI (match_operand:GPI 1 "register_operand" "%r,r,w")
+ (match_operand:GPI 2 "aarch64_logical_operand" "r,<lconst>,w")))]
""
- "<logical>\\t%<w>0, %<w>1, %<w>2"
- [(set_attr "type" "logic_reg,logic_imm")]
+ "@
+ <logical>\\t%<w>0, %<w>1, %<w>2
+ <logical>\\t%<w>0, %<w>1, %<w>2
+ <logical>\\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>"
+ [(set_attr "type" "logic_reg,logic_imm,neon_logic")
+ (set_attr "simd" "*,*,yes")]
)
;; zero_extend version of above
@@ -2734,11 +2738,14 @@
)
(define_insn "one_cmpl<mode>2"
- [(set (match_operand:GPI 0 "register_operand" "=r")
- (not:GPI (match_operand:GPI 1 "register_operand" "r")))]
+ [(set (match_operand:GPI 0 "register_operand" "=r,w")
+ (not:GPI (match_operand:GPI 1 "register_operand" "r,w")))]
""
- "mvn\\t%<w>0, %<w>1"
- [(set_attr "type" "logic_reg")]
+ "@
+ mvn\\t%<w>0, %<w>1
+ mvn\\t%0.8b, %1.8b"
+ [(set_attr "type" "logic_reg,neon_logic")
+ (set_attr "simd" "*,yes")]
)
(define_insn "*one_cmpl_<optab><mode>2"
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 3203c3da7e293d566d1ea329856cbef8fb73a825..b7f1d5709eeda0362117f7de3800b99048352225 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -401,7 +401,8 @@
(V2SI "8b") (V4SI "16b")
(V2DI "16b") (V2SF "8b")
(V4SF "16b") (V2DF "16b")
- (DI "8b") (DF "8b")])
+ (DI "8b") (DF "8b")
+ (SI "8b")])
;; Define element mode for each vector mode.
(define_mode_attr VEL [(V8QI "QI") (V16QI "QI")
