For this create a new mode_attr "hH".
Also change "i" constraints on the shift amount to "n", which better
describes what it really is (GCC takes the integer value of these
operands and does arithmetic on them; symbolic constants will not work
here).
Also merge the "dot" insns with the corresponding splitters. To do
this, don't allow the dot insns for CBE non-microcode mode at all
(it previously would just split it back always).
Bootstrapped and tested on powerpc64-linux, {-m64,-m64/-mtune=power8,
-m32,-m32/-mpowerpc64}, no regressions. Okay to apply?
Segher
2014-06-21 Segher Boessenkool <seg...@kernel.crashing.org>
gcc/
* config/rs6000/rs6000.md ("hH"): New define_mode_attr.
(lshrsi3, two anonymous define_insns and define_splits,
lshrdi3, *lshrdi3_internal1, *lshrdi3_internal2 and split,
*lshrdi3_internal3 and split): Delete, merge into...
(lshr<mode>3, lshr<mode>3_dot, lshr<mode>3_dot2): New.
(*lshrsi3_64): Fix formatting. Replace "i" by "n".
---
gcc/config/rs6000/rs6000.md | 183 ++++++++++++--------------------------------
1 file changed, 47 insertions(+), 136 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 9d92d8f..f023162 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -438,6 +438,9 @@ (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
;; ISEL/ISEL64 target selection
(define_mode_attr sel [(SI "") (DI "64")])
+;; Bitmask for shift instructions
+(define_mode_attr hH [(SI "h") (DI "H")])
+
;; Suffix for reload patterns
(define_mode_attr ptrsize [(SI "32bit")
(DI "64bit")])
@@ -4536,92 +4539,82 @@ (define_split
(const_int 0)))]
"")
-(define_insn "lshrsi3"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
+
+(define_insn "lshr<mode>3"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
+ (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
+ (match_operand:GPR 2 "reg_or_cint_operand" "r,n")))]
""
"@
- srw %0,%1,%2
- srwi %0,%1,%h2"
+ sr<wd> %0,%1,%2
+ sr<wd>i %0,%1,%<hH>2"
[(set_attr "type" "shift")
(set_attr "var_shift" "yes,no")])
(define_insn "*lshrsi3_64"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:DI
+ (zero_extend:DI
(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
+ (match_operand:SI 2 "reg_or_cint_operand" "r,n"))))]
"TARGET_POWERPC64"
"@
- srw %0,%1,%2
- srwi %0,%1,%h2"
+ srw %0,%1,%2
+ srwi %0,%1,%h2"
[(set_attr "type" "shift")
(set_attr "var_shift" "yes,no")])
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand"
"r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand"
"r,i,r,i"))
+(define_insn_and_split "*lshr<mode>3_dot"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
+ (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand"
"r,r,r,r")
+ (match_operand:GPR 2 "reg_or_cint_operand"
"r,n,r,n"))
(const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r,r,r"))]
- "TARGET_32BIT"
+ (clobber (match_scratch:GPR 0 "=r,r,r,r"))]
+ "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
"@
- srw. %3,%1,%2
- srwi. %3,%1,%h2
+ sr<wd>. %0,%1,%2
+ sr<wd>i. %0,%1,%<hH>2
#
#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (lshiftrt:GPR (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 3)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ ""
[(set_attr "type" "shift")
(set_attr "var_shift" "yes,no,yes,no")
(set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))]
- "TARGET_32BIT && reload_completed"
- [(set (match_dup 3)
- (lshiftrt:SI (match_dup 1) (match_dup 2)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn ""
+(define_insn_and_split "*lshr<mode>3_dot2"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand"
"r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand"
"r,i,r,i"))
+ (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand"
"r,r,r,r")
+ (match_operand:GPR 2 "reg_or_cint_operand"
"r,n,r,n"))
(const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
- (lshiftrt:SI (match_dup 1) (match_dup 2)))]
- "TARGET_32BIT"
+ (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r")
+ (lshiftrt:GPR (match_dup 1)
+ (match_dup 2)))]
+ "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
"@
- srw. %0,%1,%2
- srwi. %0,%1,%h2
+ sr<wd>. %0,%1,%2
+ sr<wd>i. %0,%1,%<hH>2
#
#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (lshiftrt:GPR (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 3)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ ""
[(set_attr "type" "shift")
(set_attr "var_shift" "yes,no,yes,no")
(set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (lshiftrt:SI (match_dup 1) (match_dup 2)))]
- "TARGET_32BIT && reload_completed"
- [(set (match_dup 0)
- (lshiftrt:SI (match_dup 1) (match_dup 2)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -7895,88 +7888,6 @@ (define_split
(const_int 0)))]
"")
-(define_expand "lshrdi3"
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" "")))]
- "TARGET_POWERPC64"
- "")
-
-(define_insn "*lshrdi3_internal1"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
- "TARGET_POWERPC64"
- "@
- srd %0,%1,%2
- srdi %0,%1,%H2"
- [(set_attr "type" "shift")
- (set_attr "var_shift" "yes,no")])
-
-(define_insn "*lshrdi3_internal2"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand"
"r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand"
"r,i,r,i"))
- (const_int 0)))
- (clobber (match_scratch:DI 3 "=r,r,r,r"))]
- "TARGET_64BIT "
- "@
- srd. %3,%1,%2
- srdi. %3,%1,%H2
- #
- #"
- [(set_attr "type" "shift")
- (set_attr "var_shift" "yes,no,yes,no")
- (set_attr "dot" "yes")
- (set_attr "length" "4,4,8,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:DI 3 ""))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 3)
- (lshiftrt:DI (match_dup 1) (match_dup 2)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn "*lshrdi3_internal3"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand"
"r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand"
"r,i,r,i"))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
- (lshiftrt:DI (match_dup 1) (match_dup 2)))]
- "TARGET_64BIT"
- "@
- srd. %0,%1,%2
- srdi. %0,%1,%H2
- #
- #"
- [(set_attr "type" "shift")
- (set_attr "var_shift" "yes,no,yes,no")
- (set_attr "dot" "yes")
- (set_attr "length" "4,4,8,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (lshiftrt:DI (match_dup 1) (match_dup 2)))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 0)
- (lshiftrt:DI (match_dup 1) (match_dup 2)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
(define_expand "ashrdi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
--
1.8.1.4
