On 05/29/14 16:25, Kyrill Tkachov wrote:
Hi all,
I noticed that in some of our move patterns the movw instruction is given the
mov_reg type rather than the
mov_imm type that all other uses of movw have. This patch fixes that.
Scanning through our pipeline descriptions I see that mov_imm is treated the
same way as mov_reg everywhere anyway. In the Cortex-A7 description we do have
a bit more complicated logic:
;; ALU instruction with an immediate operand can dual-issue.
(define_insn_reservation "cortex_a7_alu_imm" 2
(and (eq_attr "tune" "cortexa7")
(ior (eq_attr "type" "adr,alu_imm,alus_imm,logic_imm,logics_imm,\
mov_imm,mvn_imm,extend")
(and (eq_attr "type" "mov_reg,mov_shift,mov_shift_reg")
(not (eq_attr "length" "8")))))
"cortex_a7_ex2|cortex_a7_ex1")
In the two patterns that I change the mov_imm has a length of 4 an hence will
still use this reservation.
Thus I don't expect codegen to change at all from this patch but for future
scheduling jobs this could make a
difference.
This is ok. Well spotted.
Ramana
Tested arm-none-eabi on qemu.
Ok for trunk?
Thanks,
Kyrill
2014-05-29 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
* config/arm/thumb2.md (*thumb2_movhi_insn): Set type of movw
to mov_imm.
* config/arm/vfp.md (*thumb2_movsi_vfp): Likewise.
