The patch for PR60604 stopped nonimmediate_operand from accepting
(subreg:M (reg:N R)) for combinations that are forbidden by
REG_CANNOT_CHANGE_MODE_P, to match the existing register_operand behaviour.
This stopped rs6000's movdi pattern from accepting such subregs as a
destination (they were already not accepted as the source), which in
turn meant the result of the reload_vsx_from_gprsf splitter didn't match.
The last two patterns generated by reload_vsx_from_gprsf had the form:
(set (subreg:DI (reg:SF FPR)) (reg:DI GPR))
(set (reg:SF FPR) (... (reg:SF FPR) ...))
The target of the first move is a (subreg:DI ...) rather than (reg:DI FPR)
because the mode change is forbidden by CANNOT_CHANGE_MODE_CLASS.
But in this case the sequence is really:
(set (reg:DI FPR1) (reg:DI GPR))
(set (reg:SF FPR2) (... (reg:DI FPR1) ...))
where no mode change takes place as such. We just happen to be using
the same FPR for FPR1 and FPR2. In those circumstances gen_rtx_REG
seems more appropriate than simplify_gen_subreg.
Tested by Pat and approved by David in the PR trail. Applied.
Thanks,
Richard
gcc/
PR target/60763
* config/rs6000/vsx.md (vsx_xscvdpspn_scalar): Change input to DImode.
* config/rs6000/rs6000.md (reload_vsx_from_gprsf): Update accordingly.
Use gen_rtx_REG rather than simplify_gen_subreg for op0_di.
Index: gcc/config/rs6000/vsx.md
===================================================================
--- gcc/config/rs6000/vsx.md 2014-04-07 15:26:00.357746782 +0100
+++ gcc/config/rs6000/vsx.md 2014-04-07 15:26:00.552748458 +0100
@@ -1223,7 +1223,7 @@ (define_insn "vsx_xscvdpspn_scalar"
;; Used by direct move to move a SFmode value from GPR to VSX register
(define_insn "vsx_xscvspdpn_directmove"
[(set (match_operand:SF 0 "vsx_register_operand" "=wa")
- (unspec:SF [(match_operand:SF 1 "vsx_register_operand" "wa")]
+ (unspec:SF [(match_operand:DI 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_CVSPDPN))]
"TARGET_XSCVSPDPN"
"xscvspdpn %x0,%x1"
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md 2014-04-07 15:26:00.356746773 +0100
+++ gcc/config/rs6000/rs6000.md 2014-04-08 18:14:31.668426223 +0100
@@ -10029,13 +10029,16 @@ (define_insn_and_split "reload_vsx_from_
rtx op0 = operands[0];
rtx op1 = operands[1];
rtx op2 = operands[2];
- rtx op0_di = simplify_gen_subreg (DImode, op0, SFmode, 0);
+ /* Also use the destination register to hold the unconverted DImode value.
+ This is conceptually a separate value from OP0, so we use gen_rtx_REG
+ rather than simplify_gen_subreg. */
+ rtx op0_di = gen_rtx_REG (DImode, REGNO (op0));
rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0);
/* Move SF value to upper 32-bits for xscvspdpn. */
emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
emit_move_insn (op0_di, op2);
- emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0));
+ emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0_di));
DONE;
}
[(set_attr "length" "8")
