As recently pointed out in a thread porting libitm to aarch64, the PAGE_SIZE
and FIXED_PAGE_SIZE macros are unused. Indeed, not all of the ports actually
defined them at all.
Removed, lest they cause further confusion.
r~
* config/alpha/target.h (PAGE_SIZE, FIXED_PAGE_SIZE): Remove.
* config/arm/target.h, config/sh/target.h: Likewise.
* config/sparc/target.h, config/x86/target.h: Likewise.
diff --git a/libitm/config/alpha/target.h b/libitm/config/alpha/target.h
index 5e23c53..e33f1e1 100644
--- a/libitm/config/alpha/target.h
+++ b/libitm/config/alpha/target.h
@@ -32,10 +32,6 @@ typedef struct gtm_jmpbuf
unsigned long f[8];
} gtm_jmpbuf;
-/* Alpha generally uses a fixed page size of 8K. */
-#define PAGE_SIZE 8192
-#define FIXED_PAGE_SIZE 1
-
/* The size of one line in hardware caches (in bytes). */
#define HW_CACHELINE_SIZE 64
diff --git a/libitm/config/arm/target.h b/libitm/config/arm/target.h
index 6a1458e..a909e14 100644
--- a/libitm/config/arm/target.h
+++ b/libitm/config/arm/target.h
@@ -33,10 +33,6 @@ typedef struct gtm_jmpbuf
unsigned long pc;
} gtm_jmpbuf;
-/* ARM generally uses a fixed page size of 4K. */
-#define PAGE_SIZE 4096
-#define FIXED_PAGE_SIZE 1
-
/* ??? The size of one line in hardware caches (in bytes). */
#define HW_CACHELINE_SIZE 64
diff --git a/libitm/config/sh/target.h b/libitm/config/sh/target.h
index 6f6ae5f..fbc804c 100644
--- a/libitm/config/sh/target.h
+++ b/libitm/config/sh/target.h
@@ -35,10 +35,6 @@ typedef struct gtm_jmpbuf
#endif
} gtm_jmpbuf;
-/* SH generally uses a fixed page size of 4K. */
-#define PAGE_SIZE 4096
-#define FIXED_PAGE_SIZE 1
-
/* ??? The size of one line in hardware caches (in bytes). */
#define HW_CACHELINE_SIZE 32
diff --git a/libitm/config/sparc/target.h b/libitm/config/sparc/target.h
index b127fa4..309dac1 100644
--- a/libitm/config/sparc/target.h
+++ b/libitm/config/sparc/target.h
@@ -29,10 +29,6 @@ typedef struct gtm_jmpbuf
unsigned long pc;
} gtm_jmpbuf;
-/* UltraSPARC processors generally use a fixed page size of 8K. */
-#define PAGE_SIZE 8192
-#define FIXED_PAGE_SIZE 1
-
/* The size of one line in hardware caches (in bytes). We use the primary
cache line size documented for the UltraSPARC T1/T2. */
#define HW_CACHELINE_SIZE 16
diff --git a/libitm/config/x86/target.h b/libitm/config/x86/target.h
index 392db48..78a58e7 100644
--- a/libitm/config/x86/target.h
+++ b/libitm/config/x86/target.h
@@ -52,10 +52,6 @@ typedef struct gtm_jmpbuf
/* x86 doesn't require strict alignment for the basic types. */
#define STRICT_ALIGNMENT 0
-/* x86 uses a fixed page size of 4K. */
-#define PAGE_SIZE 4096
-#define FIXED_PAGE_SIZE 1
-
/* The size of one line in hardware caches (in bytes). */
#define HW_CACHELINE_SIZE 64
