Hans-Peter Nilsson <h...@bitrange.com> writes:
> On Fri, 14 Feb 2014, Jakub Jelinek wrote:
>> On Fri, Feb 14, 2014 at 10:37:03AM -0700, Jeff Law wrote:
>> > On 02/13/14 03:54, Richard Sandiford wrote:
>> > >Richard Sandiford <rsand...@linux.vnet.ibm.com> writes:
>> > >>Hans-Peter Nilsson <h...@bitrange.com> writes:
>> > >>>On Tue, 4 Feb 2014, Rainer Orth wrote:
>> > >>>>AFAICT the gcc.dg/binop-xor1.c test is XPASSing everywhere since about
>> > >>>>20131114:
>> > >>>
>> > >>>Bah, missing analysis. "Everywhere" does not include cris-elf,
>> > >>>powerpc64-unknown-linux-gnu, m68k-unknown-linux-gnu,
>> > >>>s390x-ibm-linux-gnu, powerpc-ibm-aix7.1.0.0.
>> > >>
>> > >>Based on this list I'm guessing it's another BRANCH_COST==1
>> > >
>> > >BRANCH_COST==1 || !LOGICAL_OP_NON_SHORT_CIRCUIT
>> > ISTM that we ought to have a dejagnu test which we can use to ignore
>> > or otherwise change the expected output on these targets.
>> >
>> > We could try and be clever and determine it from compiler output, or
>> > somehow arrange for GCC to make that information available to
>> > dejagnu. But by far the easiest way is just a list of targets.
>>
>> Yeah, the BRANCH_COST and/or LOGICAL_OP_NON_SHORT_CIRCUIT value could e.g.
>> be emitted in some comment in selected tree dump if details are requested
>> (say
>> -fdump-tree-gimple-details) and then an effective target can check for that
>> easily.
>
> I've been thinking along those lines (though a RTL dump will be
> somewhat more appropriate). A target list will be insufficient
> when the branch cost etc. depends on compiler options.
Or I suppose we could add some predefined macros (perhaps again only
if a particular option is selected).
But I don't have a problem with a list of targets either. It's certainly
good enough for LOGICAL_OP_NON_SHORT_CIRCUIT on MIPS, which is always 0.
So this patch just moves the !LOGICAL_OP_NON_SHORT_CIRCUIT target lists
to a logical_op_short_circuit target, as H-P suggested.
In the case of avr*-*-* the !LOGICAL_OP_NON_SHORT_CIRCUIT comes from
BRANCH_COST being 0 while for arc*-*-* and arm_cortex_m it comes
from an explicit back-end definition.
I marked binop-xor1.c as an XFAIL rather than a skip because using ^
might be an improvement even for logical_op_short_circuit.
I didn't do anything about the branch cost since this is enough for MIPS.
Tested on x86_64-linux-gnu (including checking that the tests were still
being run) and mipsisa64-sde-elf. OK to install?
Thanks,
Richard
gcc/testsuite/
* lib/target-supports.exp
(check_effective_target_logical_op_short_circuit): New procedure.
* gcc.dg/binop-xor1.c: XFAIL for logical_op_short_circuit.
* gcc.dg/tree-ssa/forwprop-28.c: Use logical_op_short_circuit
instead of mips*-*-*, arc*-*-*, avr*-*-* and arm_cortex_m tests.
* gcc.dg/tree-ssa/vrp47.c: Likewise.
* gcc.dg/tree-ssa/vrp87.c: Likewise.
* gcc.dg/tree-ssa/ssa-dom-thread-4.c: Likewise. Also use
logical_op_short_circuit for the alternative test, extending
it to arm_cortex_m.
Index: gcc/testsuite/lib/target-supports.exp
===================================================================
--- gcc/testsuite/lib/target-supports.exp 2014-02-15 17:51:13.001741846
+0000
+++ gcc/testsuite/lib/target-supports.exp 2014-02-15 18:02:30.053843150
+0000
@@ -5690,6 +5690,18 @@ proc check_effective_target_fenv_excepti
} "-std=gnu99"]
}
+# Return 1 if LOGICAL_OP_NON_SHORT_CIRCUIT is set to 0 for the current target.
+
+proc check_effective_target_logical_op_short_circuit {} {
+ if { [istarget mips*-*-*]
+ || [istarget arc*-*-*]
+ || [istarget avr*-*-*]
+ || [check_effective_target_arm_cortex_m] } {
+ return 1
+ }
+ return 0
+}
+
# Record that dg-final test TEST requires convential compilation.
proc force_conventional_output_for { test } {
Index: gcc/testsuite/gcc.dg/binop-xor1.c
===================================================================
--- gcc/testsuite/gcc.dg/binop-xor1.c 2014-02-15 17:51:12.970741566 +0000
+++ gcc/testsuite/gcc.dg/binop-xor1.c 2014-02-15 17:51:13.439745797 +0000
@@ -7,5 +7,5 @@ foo (int a, int b, int c)
return ((a && !b && c) || (!a && b && c));
}
-/* { dg-final { scan-tree-dump-times "\\\^" 1 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\\\^" 1 "optimized" { xfail
logical_op_short_circuit } } } */
/* { dg-final { cleanup-tree-dump "optimized" } } */
Index: gcc/testsuite/gcc.dg/tree-ssa/forwprop-28.c
===================================================================
--- gcc/testsuite/gcc.dg/tree-ssa/forwprop-28.c 2014-02-15 17:51:12.984741692
+0000
+++ gcc/testsuite/gcc.dg/tree-ssa/forwprop-28.c 2014-02-15 18:00:44.562893555
+0000
@@ -1,9 +1,7 @@
-/* { dg-do compile { target { ! "m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-*
v850*-*-* picochip*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-*
powerpc*-*-* xtensa*-*-* arc*-*-* hppa*-*-* mips*-*-*"} } } */
+/* Setting LOGICAL_OP_NON_SHORT_CIRCUIT to 0 leads to two conditional jumps
+ when evaluating an && condition. VRP is not able to optimize this. */
+/* { dg-do compile { target { ! { logical_op_short_circuit || { m68k*-*-*
mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* picochip*-*-* moxie*-*-* cris*-*-*
m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* } } } } } */
/* { dg-options "-O2 -fdump-tree-forwprop1" } */
-/* Skip on ARM Cortex-M, where LOGICAL_OP_NON_SHORT_CIRCUIT is set to false,
- leading to two conditional jumps when evaluating an && condition. Forwprop1
- is not able to optimize this. */
-/* { dg-skip-if "" { arm_cortex_m } } */
extern char *frob (void);
extern _Bool testit (void);
Index: gcc/testsuite/gcc.dg/tree-ssa/vrp47.c
===================================================================
--- gcc/testsuite/gcc.dg/tree-ssa/vrp47.c 2014-02-15 17:51:12.999741828
+0000
+++ gcc/testsuite/gcc.dg/tree-ssa/vrp47.c 2014-02-15 17:52:45.578576970
+0000
@@ -1,15 +1,11 @@
-/* Skip on MIPS/ARC, where LOGICAL_OP_NON_SHORT_CIRCUIT inhibits the setcc
+/* Setting LOGICAL_OP_NON_SHORT_CIRCUIT to 0 inhibits the setcc
optimizations that expose the VRP opportunity. */
-/* Skip on S/390 and avr. Lower values in BRANCH_COST lead to two conditional
+/* Skip on S/390. Lower values in BRANCH_COST lead to two conditional
jumps when evaluating an && condition. VRP is not able to optimize
this. */
-/* { dg-do compile { target { ! "mips*-*-* arc*-*-* s390*-*-* avr-*-*
mn10300-*-* hppa*-*-*" } } } */
+/* { dg-do compile { target { ! { logical_op_short_circuit || { s390*-*-*
mn10300-*-* hppa*-*-* } } } } } */
/* { dg-options "-O2 -fdump-tree-vrp1 -fdump-tree-dom1 -fdump-tree-vrp2" } */
/* { dg-additional-options "-march=i586" { target { { i?86-*-* x86_64-*-* } &&
ia32 } } } */
-/* Skip on ARM Cortex-M, where LOGICAL_OP_NON_SHORT_CIRCUIT is set to false,
- leading to two conditional jumps when evaluating an && condition. VRP is
- not able to optimize this. */
-/* { dg-skip-if "" { arm_cortex_m } } */
int h(int x, int y)
{
Index: gcc/testsuite/gcc.dg/tree-ssa/vrp87.c
===================================================================
--- gcc/testsuite/gcc.dg/tree-ssa/vrp87.c 2014-02-15 17:51:13.000741837
+0000
+++ gcc/testsuite/gcc.dg/tree-ssa/vrp87.c 2014-02-15 17:56:57.075845605
+0000
@@ -1,11 +1,8 @@
-/* { dg-do compile { target { ! "m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-*
v850*-*-* picochip*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-*
powerpc*-*-* xtensa*-*-* arc*-*-* hppa*-*-* mips*-*-*"} } } */
+/* Setting LOGICAL_OP_NON_SHORT_CIRCUIT to 0 leads to two conditional jumps
+ when evaluating an && condition. VRP is not able to optimize this. */
+/* { dg-do compile { target { ! { logical_op_short_circuit || { m68k*-*-*
mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* picochip*-*-* moxie*-*-* cris*-*-*
m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* } } } } } */
/* { dg-options "-O2 -fdump-tree-vrp2-details -fdump-tree-cddce2-details" } */
-/* { dg-additional-options "-mbranch-cost=2" { target mips*-*-* avr-*-* } } */
-/* Skip on ARM Cortex-M, where LOGICAL_OP_NON_SHORT_CIRCUIT is set to false,
- leading to two conditional jumps when evaluating an && condition. VRP is
- not able to optimize this. */
-/* { dg-skip-if "" { arm_cortex_m } } */
struct bitmap_head_def;
typedef struct bitmap_head_def *bitmap;
Index: gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-4.c
===================================================================
--- gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-4.c 2014-02-15
17:51:12.999741828 +0000
+++ gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-4.c 2014-02-15
17:51:13.439745797 +0000
@@ -59,10 +59,8 @@ bitmap_ior_and_compl (bitmap dst, const_
code we missed the edge when the first conditional is false
(b_elt is zero, which means the second conditional is always
zero. */
-/* ARM Cortex-M defined LOGICAL_OP_NON_SHORT_CIRCUIT to false,
- so skip below test. */
-/* { dg-final { scan-tree-dump-times "Threaded" 3 "dom1" { target { ! { {
mips*-*-* avr-*-* arc*-*-* } || { arm_cortex_m } } } } } } */
-/* MIPS defines LOGICAL_OP_NON_SHORT_CIRCUIT to 0, so we split both
+/* { dg-final { scan-tree-dump-times "Threaded" 3 "dom1" { target { !
logical_op_short_circuit } } } } */
+/* On targets that define LOGICAL_OP_NON_SHORT_CIRCUIT to 0, we split both
"a_elt || b_elt" and "b_elt && kill_elt" into two conditions each,
rather than using "(var1 != 0) op (var2 != 0)". Also, as on other targets,
we duplicate the header of the inner "while" loop. There are then
@@ -78,9 +76,6 @@ bitmap_ior_and_compl (bitmap dst, const_
-> "kill_elt->indx == b_elt->indx" in the second condition,
skipping the known-true "b_elt && kill_elt" in the second
condition. */
-/* Likewise for arc. */
-/* For avr, BRANCH_COST is by default 0, so the default
- LOGICAL_OP_NON_SHORT_CIRCUIT definition also computes as 0. */
-/* { dg-final { scan-tree-dump-times "Threaded" 4 "dom1" { target mips*-*-*
avr-*-* arc*-*-* } } } */
+/* { dg-final { scan-tree-dump-times "Threaded" 4 "dom1" { target
logical_op_short_circuit } } } */
/* { dg-final { cleanup-tree-dump "dom1" } } */
