Hi,
This patch fixes shift right pattern, as it failed on -O0 after shift
right patch. The reason was unnecessary movement of immediate value to
a register due to type mismatch.
Patch is tested not to cause any additional regressions.
Could someone, please, approve and commit this patch, as I do not have
the rights to do so?
Kind regards,
Alex
2014-01-28 Alex Velenko <alex.vele...@arm.com>
gcc/
* config/aarch64/aarch64-simd.md (aarch64_ashr_simddi): Fixed.
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 7378da9122d550f869c3e830e3e5a7681e7581f6..4dffb59e856aeaafb79007255d3b91a73ef1ef13 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -689,7 +689,7 @@
(define_expand "aarch64_ashr_simddi"
[(match_operand:DI 0 "register_operand" "=w")
(match_operand:DI 1 "register_operand" "w")
- (match_operand:QI 2 "aarch64_shift_imm64_di" "")]
+ (match_operand:SI 2 "aarch64_shift_imm64_di" "")]
"TARGET_SIMD"
{
if (INTVAL (operands[2]) == 64)
