[PATCH][AArch64] Wire up Cortex-A57 rtx costs

[Kyrill Tkachov]

Hi all,

This patch wires up the aarch64 backend to use the Cortex-A57 rtx costs table 
that is proposed at
http://gcc.gnu.org/ml/gcc-patches/2014-01/msg01954.html
It also sets the generic tuning to use the Cortex-A57 costs since they are more 
sensible for aarch64 systems than the generic ones that were originally written 
with aarch32 code generation in mind.

Tested aarch64-none-elf on a model.

Ok for trunk once the prerequisite goes in?

Thanks,
Kyrill

2014-01-30  Kyrylo Tkachov  <kyrylo.tkac...@arm.com>

    * config/aarch64/aarch64-cores.def (cortex-a57): Use cortexa57
    tuning struct.
    (cortex-a57.cortex-a53): Likewise.
    * config/aarch64/aarch64.c (cortexa57_tunings): New tuning struct.
commit 780da554b322ab1c54cc662849950adb1181cacb
Author: Kyrylo Tkachov <kyrylo.tkac...@arm.com>
Date:   Fri Jan 24 11:36:02 2014 +0000

    [AArch64] Wire up A57 costs

diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
index a41d7d9..4db63d6 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -35,8 +35,8 @@
 /* V8 Architecture Processors.  */
 
 AARCH64_CORE("cortex-a53",  cortexa53, cortexa53, 8,  AARCH64_FL_FPSIMD, cortexa53)
-AARCH64_CORE("cortex-a57",  cortexa15, cortexa15, 8,  AARCH64_FL_FPSIMD, generic)
+AARCH64_CORE("cortex-a57",  cortexa15, cortexa15, 8,  AARCH64_FL_FPSIMD, cortexa57)
 
 /* V8 big.LITTLE implementations.  */
 
-AARCH64_CORE("cortex-a57.cortex-a53",  cortexa57cortexa53, cortexa53, 8,  AARCH64_FL_FPSIMD, generic)
+AARCH64_CORE("cortex-a57.cortex-a53",  cortexa57cortexa53, cortexa53, 8,  AARCH64_FL_FPSIMD, cortexa57)
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 5867f75..aca4366 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -235,6 +235,16 @@ static const struct tune_params cortexa53_tunings =
   NAMED_PARAM (issue_rate, 2)
 };
 
+static const struct tune_params cortexa57_tunings =
+{
+  &cortexa57_extra_costs,
+  &generic_addrcost_table,
+  &generic_regmove_cost,
+  &generic_vector_cost,
+  NAMED_PARAM (memmov_cost, 4),
+  NAMED_PARAM (issue_rate, 3)
+};
+
 /* A processor implementing AArch64.  */
 struct processor
 {