This patch marks the prefetch intrinsics as scheduling barriers.
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b5487ae..39543a1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2014-01-25 Walter Lee <w...@tilera.com> + * config/tilegx/tilegx.c (tilegx_expand_builtin): Set + PREFETCH_SCHEDULE_BARRIER_P to true for prefetches. + * config/tilepro/tilepro.c (tilepro_expand_builtin): Ditto. + +2014-01-25 Walter Lee <w...@tilera.com> + * config/tilepro/tilepro.md (ctzdi2): Use register_operand predicate. (clzdi2): Ditto. diff --git a/gcc/config/tilegx/tilegx.c b/gcc/config/tilegx/tilegx.c index 85a46f7..c168621 100644 --- a/gcc/config/tilegx/tilegx.c +++ b/gcc/config/tilegx/tilegx.c @@ -3570,6 +3570,12 @@ tilegx_expand_builtin (tree exp, } if (!pat) return NULL_RTX; + + /* If we are generating a prefetch, tell the scheduler not to move + it around. */ + if (GET_CODE (pat) == PREFETCH) + PREFETCH_SCHEDULE_BARRIER_P (pat) = true; + emit_insn (pat); if (nonvoid) diff --git a/gcc/config/tilepro/tilepro.c b/gcc/config/tilepro/tilepro.c index 615d490..74f8800 100644 --- a/gcc/config/tilepro/tilepro.c +++ b/gcc/config/tilepro/tilepro.c @@ -3184,6 +3184,12 @@ tilepro_expand_builtin (tree exp, } if (!pat) return NULL_RTX; + + /* If we are generating a prefetch, tell the scheduler not to move + it around. */ + if (GET_CODE (pat) == PREFETCH) + PREFETCH_SCHEDULE_BARRIER_P (pat) = true; + emit_insn (pat); if (nonvoid)