[committed] TILEPro: fix ctzdi2, clzdi2, and ffsdi2 patterns.

[Walter Lee]

This patch fixes the predicates for the ctzdi2, clzdi2, and ffsdi2.
reg_or_0_operand is a 32-bit predicate so it will never match a DI
operand.  It's sufficient to use register_operand.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9306621..b5487ae 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,12 @@
 2014-01-25  Walter Lee  <w...@tilera.com>
 
+       * config/tilepro/tilepro.md (ctzdi2): Use register_operand
+       predicate.
+       (clzdi2): Ditto.
+       (ffsdi2): Ditto.
+
+2014-01-25  Walter Lee  <w...@tilera.com>
+
        * config/tilegx/tilegx.c (tilegx_expand_to_rtl_hook): New.
        (TARGET_EXPAND_TO_RTL_HOOK): Define.
 
diff --git a/gcc/config/tilepro/tilepro.md b/gcc/config/tilepro/tilepro.md
index adf49ba..314dd90 100644
--- a/gcc/config/tilepro/tilepro.md
+++ b/gcc/config/tilepro/tilepro.md
@@ -795,7 +795,7 @@
 
 (define_expand "ctzdi2"
   [(set (match_operand:DI 0 "register_operand" "")
-       (ctz:DI (match_operand:DI 1 "reg_or_0_operand" "")))]
+       (ctz:DI (match_operand:DI 1 "register_operand" "")))]
   ""
 {
   rtx lo, hi, ctz_lo, ctz_hi, ctz_hi_plus_32, result;
@@ -823,7 +823,7 @@
 
 (define_expand "clzdi2"
   [(set (match_operand:DI 0 "register_operand" "")
-       (clz:DI (match_operand:DI 1 "reg_or_0_operand" "")))]
+       (clz:DI (match_operand:DI 1 "register_operand" "")))]
   ""
 {
   rtx lo, hi, clz_lo, clz_hi, clz_lo_plus_32, result;
@@ -851,7 +851,7 @@
 
 (define_expand "ffsdi2"
   [(set (match_operand:DI 0 "register_operand" "")
-       (ffs:DI (match_operand:DI 1 "reg_or_0_operand" "")))]
+       (ffs:DI (match_operand:DI 1 "register_operand" "")))]
   ""
 {
   rtx lo, hi, ctz_lo, ctz_hi, ctz_hi_plus_32, ctz, ctz_plus_1,ctz_cond;