On Tue, Jan 21, 2014 at 7:52 PM, Kirill Yukhin <kirill.yuk...@gmail.com> wrote: > Hello, > This is non-trivial part of the patch. > >> On 15 Jan 20:53, Uros Bizjak wrote: >> On Tue, Jan 14, 2014 at 7:13 AM, Kirill Yukhin <kirill.yuk...@gmail.com> >> wrote: >> Did you try to add DF/SF mode to the unspec? I am not familiar with >> this insn, but shouldn't the mode of mem access be somehow similar to >> the avx512f_scattersi<mode> access? > avx512f_scattersi<mode> is different in its appearence. > It has explicit type of destination which discriminates SF/DF modes. > Prefetches > has no such. > >> Also, you can use double macroization with MODEF iterator for SF and DFmode. > I think I cannot. Because DF/SF types of the insn incurs different vidx > iterators. > E.g.: > Currently we have for SF: > (define_expand "avx512pf_scatterpf<VI48_512:mode>sf" > [(unspec > [(match_operand:<avx512fmaskmode> 0 "register_or_constm1_operand") > (mem:SF > (match_par_dup 5 > [(match_operand 2 "vsib_address_operand") > (match_operand:VI48_512 1 "register_operand") > (match_operand:SI 3 "const1248_operand")])) > (match_operand:SI 4 "const_0_to_1_operand")] > UNSPEC_SCATTER_PREFETCH)] > > and for DF: > (define_expand "avx512pf_scatterpf<mode>df" > [(unspec > [(match_operand:<avx512fmaskmode> 0 "register_or_constm1_operand") > (mem:DF > (match_par_dup 5 > [(match_operand 2 "vsib_address_operand") > (match_operand:VI4_256_8_512 1 "register_operand") > (match_operand:SI 3 "const1248_operand")])) > (match_operand:SI 4 "const_0_to_1_operand")] > UNSPEC_SCATTER_PREFETCH)] > > We have this correspondence between, say, main and index modes: > SF -> (V16SI, V8DI) > DF -> (V8SI , V8DI)
It looks to me that you should use V16SF and V8DF instead of SF and DF modes here. Other than this, the patch looks OK to me. Please wait a day if Jakub has any remark here. Thanks, Uros.
