On 13 January 2014 19:27, Vidya Praveen <vidyaprav...@arm.com> wrote: > Hello, > > This patch adds support to the SISD variants of SCVTF/UCVTF instructions. > This also refactors the existing support for floating point instruction > variants of SCVTF/UCVTF in order to direct the instruction selection based > on the constraints. Given that the floating-point variations supports > inequal width convertions (SI to DF and DI to SF), new mode iterator w1 and > w2 have been introduced and fcvt_target,FCVT_TARGET have been extended to > support non vector type. Since this patch changes the existing patterns, the > testcase includes tests for both SISD and floating point variations of the > instructions. > > Tested for aarch64-none-elf. > > OK for trunk?
OK but wait for stage-1. /Marcus
