On Tue, Jan 14, 2014 at 02:49:30PM +0000, Richard Earnshaw wrote:
> On 14/01/14 14:32, Jakub Jelinek wrote:
> > Anyway, the above is really a simple case, and I'd call it a
> > backend bug if it isn't able to generate good code out of that.
>
> Exactly which back-end pass are you expecting to simplify
>
> (set (subreg:SI (reg:HI 1) 0) (and:SI (subreg:SI (reg:HI 0) 0)
> (const_int 2)))
Well, already at the expansion time you know here that & 2 is zero-extended,
so you can/should emit here (set (reg:SI 1)) (and:SI (subreg:SI (reg:HI 0) 0)
(const_int 2)))
instead. And/or combiner, and/or what Kugan has been working on,
to use the remembered SSA_NAME range info during expansion.
And/or, as I said earlier, we can have a type promotion pass driven by
backend properties. But not narrowing types anywhere will mean say
the various issues mentioned in PR45397. For vectorizations we want to
decrease the number of different type widths in a loop as much as possible,
etc.
Jakub
