On Mon, Dec 23, 2013 at 5:10 AM, H.J. Lu <hjl.to...@gmail.com> wrote:
> On Sun, Dec 22, 2013 at 11:11:12PM +0100, Uros Bizjak wrote:
>> On Sun, Dec 22, 2013 at 8:28 PM, H.J. Lu <hjl.to...@gmail.com> wrote:
>>
>> >> > > >>> > Perhaps we should add sandybridge, ivybridge and haswell
>> >> > > >>> > aliases for
>> >> > > >>> > corei7-avx, core-avx-i, core-avx2? I mean, it is a nightmare
>> >> > > >>> > to remember
>> >> > > >>> > which one has the i7 in and which doesn't even for me.
>> >> > > >>>
>> >> > > >>> Yes please, I think this is a good idea.
>> >> > > >>
>> >> > > >> I've added aliases for haswell, sandybridge, ivybridge, bonnell,
>> >> > > >> nehalem and silvermont.
>> >> > > >>
>> >> > > > Old names, like corei7, core-avx-i, atom, .. don't have precise
>> >> > > > description for the processor. I think gcc driver should keep
>> >> > > > accepting them. But they should be marked as undocumented
>> >> > > > or deprecated. They should be removed from documentation.
>> >> > >
>> >> > > How about we leave these as -march=... to refer to the architecture,
>> >> > > and reintroduce -mcpu= to refer to the exact cpu? Internally, the
>> >> > > -mcpu would use some architecture specific base PTA_ attributes (as
>> >> > > Jakub suggested) and would add some fine-tuning PTA_ attributes, based
>> >> > > on -mcpu selection. This way, -march stays as is, and can still be
>> >> > > used for some generally distributed binaries.
>> >> >
>> >> > -mcpu is problematic, because it means various things among different
>> >> > targets, and even on i?86/x86_64 it used to mean something already in
>> >> > the
>> >> > past. Sometimes -mcpu= is what -march= is now on i?86/x86_64, sometimes
>> >> > what -mtune= is. I'd say we don't need to deprecate anything, just add
>> >> > new
>> >> > aliases for the sometimes harder to remember names. But everything just
>> >> > IMHO.
>> >> >
>> >> > Jakub
>> >>
>> >> There are many problems with the current -march=xxx/-mtune=xxx for
>> >> Intel processors, which aren't faults of GCC:
>> >>
>> >> 1. Atom processors can be Bonnell or Silvermont processors. -mtune=atom
>> >> may not optimize for the Atom CPU being targeted.
>> >> 2. Core I7 processors can be Nehalem, Westmere, Sandy Bridge, Ivy Bridge,
>> >> Haswell or Broadwell. It is hard to tell which -mtune= to use for saying
>> >> Core i7-3820QM.
>> >> 3. There are Core i3/i5, Xeon, Celeron, Pentium processors which aren't
>> >> called Core I7. They may be Nehalem, Westmere, Sandy Bridge, Ivy Bridge,
>> >> Haswell or even Silvermont.
>> >>
>> >> We should move away from corei7, corei7-avx, core-avx-i, core-avx2, atom.
>> >> Instead, we should use the actual processor names. We must accept those
>> >> old names. But we should remove them from GCC manual to avoid any
>> >> confusions. This patch adds -march=/mtune={nehalem,westmere,sandybridge,
>> >> ivybridge,haswell,broadwell,bonnell,silvermont}. It also adds
>> >> --with-arch=/--with-cpu= support as well as adds "ivybridge", "haswell",
>> >> "bonnell", "silvermont" to multi-arch function versioning.
>> >>
>> >> Any comments?
>> >
>> > This is the updated patch to add PTA_XXX as well as fix
>> >
>> > http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59580
>> >
>> > to properly check --with-arch=/--with-cpu= options. Now we only need
>> > to add a new processor to x86_64_archs, which will enable its
>> > --with-arch=/--with-cpu= support.
>> >
>> >
>> > H.J.
>> > ---
>> > gcc/
>> >
>> > 2013-12-22 H.J. Lu <hongjiu...@intel.com>
>> > Tocar Ilya <ilya.to...@intel.com>
>> >
>> > * config.gcc (x86_archs): New variable.
>> > (x86_64_archs): Likewise.
>> > (x86_cpus): Likewise.
>> > Use $x86_archs, $x86_64_archs and $x86_cpus to check valid
>> > --with-arch/--with-cpu= options.
>> > Support --with-arch=/--with-cpu={nehalem,westmere,
>> > sandybridge,ivybridge,haswell,broadwell,bonnell,silvermont}.
>> >
>> > * config/i386/core2.md: Replace corei7 with nehalem.
>> >
>> > * config/i386/driver-i386.c (host_detect_local_cpu): Use nehalem,
>> > westmere, sandybridge, ivybridge, haswell, bonnell, silvermont
>> > for cpu names.
>> >
>> > * config/i386/i386-c.c (ix86_target_macros_internal): Replace
>> > PROCESSOR_COREI7, PROCESSOR_COREI7_AVX, PROCESSOR_ATOM,
>> > PROCESSOR_SLM with PROCESSOR_NEHALEM, PROCESSOR_SANDYBRIDGE,
>> > PROCESSOR_BONNELL, PROCESSOR_SILVERMONT. Define
>> > __nehalem/__nehalem__, __sandybridge/__sandybridge__,
>> > __haswell/__haswell__, __tune_nehalem__, __tune_sandybridge__,
>> > __tune_haswell__, __bonnell/__bonnell__,
>> > __silvermont/__silvermont__, __tune_bonnell__,
>> > __tune_silvermont__.
>> >
>> > * config/i386/i386.c (m_COREI7): Renamed to ...
>> > (m_NEHALEM): This.
>> > (m_COREI7_AVX): Renamed to ...
>> > (m_SANDYBRIDGE): This.
>> > (m_ATOM): Renamed to ...
>> > (m_BONNELL): This.
>> > (m_SLM): Renamed to ...
>> > (m_SILVERMONT): This.
>> > (m_CORE_ALL): Updated.
>> > (cpu_names): Add "nehalem", "westmere", "sandybridge",
>> > "ivybridge", "haswell", "broadwell", "bonnell", "silvermont".
>> > (PTA_CORE2): New.
>> > (PTA_NEHALEM): Likewise.
>> > (PTA_WESTMERE): Likewise.
>> > (PTA_SANDYBRIDGE): Likewise.
>> > (PTA_IVYBRIDGE): Likewise.
>> > (PTA_HASWELL): Likewise.
>> > (PTA_BROADWELL): Likewise.
>> > (PTA_BONNELL): Likewise.
>> > (PTA_SILVERMONT): Likewise.
>> > (ix86_option_override_internal): Use new PTA_XXX. Add nehalem,
>> > westmere, sandybridge, ivybridge, haswell, bonnell, silvermont.
>> > (ix86_lea_outperforms): Updated.
>> > (ix86_issue_rate): Likewise.
>> > (ix86_adjust_cost): Likewise.
>> > (ia32_multipass_dfa_lookahead): Likewise.
>> > (do_reorder_for_imul): Likewise.
>> > (swap_top_of_ready_list): Likewise.
>> > (ix86_sched_reorder): Likewise.
>> > (ix86_sched_init_global): Likewise.
>> > (get_builtin_code_for_version): Likewise. Handle PROCESSOR_HASWELL
>> > and PROCESSOR_SILVERMONT.
>> > (processor_model): Replace M_INTEL_ATOM, M_INTEL_SLM with
>> > M_INTEL_BONNELL, M_INTEL_SILVERMONT. Add M_INTEL_COREI7_IVYBRIDGE
>> > and M_INTEL_COREI7_HASWELL.
>> > (arch_names_table): Updated. Add "ivybridge", "haswell",
>> > "bonnell", "silvermont".
>> >
>> > * config/i386/i386.h (TARGET_COREI7): Removed.
>> > (TARGET_COREI7_AVX): Likewise.
>> > (TARGET_ATOM): Likewise.
>> > (TARGET_SLM): Likewise.
>> > (TARGET_NEHALEM): New.
>> > (TARGET_SANDYBRIDGE): Likewise.
>> > (TARGET_BONNELL): Likewise.
>> > (TARGET_SILVERMONT): Likewise.
>> > (target_cpu_default): Add TARGET_CPU_DEFAULT_nehalem,
>> > TARGET_CPU_DEFAULT_westmere, TARGET_CPU_DEFAULT_sandybridge,
>> > TARGET_CPU_DEFAULT_ivybridge, TARGET_CPU_DEFAULT_broadwell,
>> > TARGET_CPU_DEFAULT_bonnell, TARGET_CPU_DEFAULT_silvermont.
>> > (processor_type): Replace PROCESSOR_COREI7, PROCESSOR_COREI7_AVX,
>> > PROCESSOR_ATOM, PROCESSOR_SLM with PROCESSOR_NEHALEM,
>> > PROCESSOR_SANDYBRIDGE, PROCESSOR_BONNELL, PROCESSOR_SILVERMONT.
>> >
>> > * config/i386/i386.md (cpu): Replace corei7 with nehalem.
>> >
>> > * config/i386/x86-tune.def: Updated.
>> >
>> > * doc/invoke.texi: Replace corei7, corei7-avx, core-avx-i,
>> > core-avx2, atom, slm with nehalem, sandybridge, ivybridge,
>> > haswell, bonnel, silvermont. Add westmere.
>> >
>> > libgcc/
>> >
>> > 2013-12-22 H.J. Lu <hongjiu...@intel.com>
>> >
>> > * config/i386/cpuinfo.c (processor_subtypes): Replace INTEL_ATOM,
>> > INTEL_SLM with INTEL_BONNELL, INTEL_SILVERMONT. Add
>> > INTEL_COREI7_IVYBRIDGE and INTEL_COREI7_HASWELL.
>> > (get_intel_cpu): Updated. Check Ivy Bridge and Haswell processors.
>>
>> The patch is OK for rename and addition of new aliases. Target cpu
>> changes, other than renames, should be split out to a follow-up patch
>> and coordinated with Allan's ongoing patch in this area.
>>
> ...
>> > @@ -2432,9 +2432,16 @@ static const char *const
>> > cpu_names[TARGET_CPU_DEFAULT_max] =
>> > "core2",
>> > "corei7",
>> > "corei7-avx",
>> > - "core-avx2",
>>
>> Please don't delete names..
> diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
> index b6e7d46..aafc1ac 100644
> --- a/gcc/config/i386/i386.h
> +++ b/gcc/config/i386/i386.h
> @@ -301,9 +301,11 @@ extern const struct processor_costs ix86_size_cost;
> #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
> #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
> #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
> -#define TARGET_COREI7 (ix86_tune == PROCESSOR_COREI7)
> -#define TARGET_COREI7_AVX (ix86_tune == PROCESSOR_COREI7_AVX)
> +#define TARGET_NEHALEM (ix86_tune == PROCESSOR_NEHALEM)
> +#define TARGET_SANDYBRIDGE (ix86_tune == PROCESSOR_SANDYBRIDGE)
> #define TARGET_HASWELL (ix86_tune == PROCESSOR_HASWELL)
> +#define TARGET_BONNELL (ix86_tune == PROCESSOR_BONNELL)
> +#define TARGET_SILVERMONT (ix86_tune == PROCESSOR_SILVERMONT)
> #define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC)
> #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
> #define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1)
> @@ -312,8 +314,6 @@ extern const struct processor_costs ix86_size_cost;
> #define TARGET_BDVER4 (ix86_tune == PROCESSOR_BDVER4)
> #define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1)
> #define TARGET_BTVER2 (ix86_tune == PROCESSOR_BTVER2)
> -#define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM)
> -#define TARGET_SLM (ix86_tune == PROCESSOR_SLM)
>
> /* Feature tests against the various tunings. */
> enum ix86_tune_indices {
> @@ -625,9 +625,17 @@ enum target_cpu_default
> TARGET_CPU_DEFAULT_core2,
> TARGET_CPU_DEFAULT_corei7,
> TARGET_CPU_DEFAULT_corei7_avx,
> - TARGET_CPU_DEFAULT_haswell,
> + TARGET_CPU_DEFAULT_core_avx2,
> TARGET_CPU_DEFAULT_atom,
> TARGET_CPU_DEFAULT_slm,
> + TARGET_CPU_DEFAULT_nehalem,
> + TARGET_CPU_DEFAULT_westmere,
> + TARGET_CPU_DEFAULT_sandybridge,
> + TARGET_CPU_DEFAULT_ivybridge,
> + TARGET_CPU_DEFAULT_haswell,
> + TARGET_CPU_DEFAULT_broadwell,
> + TARGET_CPU_DEFAULT_bonnell,
> + TARGET_CPU_DEFAULT_silvermont,
> TARGET_CPU_DEFAULT_intel,
>
> TARGET_CPU_DEFAULT_geode,
> @@ -2220,9 +2228,11 @@ enum processor_type
> PROCESSOR_K8,
> PROCESSOR_NOCONA,
> PROCESSOR_CORE2,
> - PROCESSOR_COREI7,
> - PROCESSOR_COREI7_AVX,
> + PROCESSOR_NEHALEM,
> + PROCESSOR_SANDYBRIDGE,
> PROCESSOR_HASWELL,
> + PROCESSOR_BONNELL,
> + PROCESSOR_SILVERMONT,
> PROCESSOR_GENERIC,
> PROCESSOR_AMDFAM10,
> PROCESSOR_BDVER1,
> @@ -2231,8 +2241,6 @@ enum processor_type
> PROCESSOR_BDVER4,
> PROCESSOR_BTVER1,
> PROCESSOR_BTVER2,
> - PROCESSOR_ATOM,
> - PROCESSOR_SLM,
> PROCESSOR_max
> };
>
When I moved PROCESSOR_BONNELL/PROCESSOR_SILVERMONT
to together with Intel entries, I forgot to update rocessor_target_table.
I checked in this patch to fix:
FAIL: gcc.dg/vect/costmodel/i386/costmodel-fast-math-vect-pr29925.c
scan-tree-dump-times vect "vectorized 1 loops" 1
FAIL: gcc.dg/vect/costmodel/i386/costmodel-vect-31.c
scan-tree-dump-times vect "vectorization not profitable" 1
FAIL: gcc.dg/vect/costmodel/i386/costmodel-vect-31.c
scan-tree-dump-times vect "vectorized 3 loops" 1
FAIL: gcc.dg/vect/costmodel/i386/costmodel-vect-68.c
scan-tree-dump-times vect "vectorized 4 loops" 1
FAIL: gcc.target/i386/avx2-cvt-2.c scan-tree-dump-times vect "note:
vectorized 1 loops in function" 6
FAIL: gcc.target/i386/avx-cvt-2.c scan-tree-dump-times vect "note:
vectorized 1 loops in function" 6
FAIL: gcc.target/i386/avx-cvt-3.c scan-tree-dump-times vect "note:
vectorized 1 loops in function" 6
FAIL: gcc.target/i386/memcpy-2.c scan-assembler-not (jmp|call)[\\t ]*memcpy
FAIL: gcc.target/i386/memcpy-3.c scan-assembler-not (jmp|call)[\\t ]*memcpy
FAIL: gcc.target/i386/pr46295.c scan-assembler-times avx_vzeroupper 1
FAIL: gcc.target/i386/sse2-cvt-2.c scan-tree-dump-times vect "note:
vectorized 1 loops in function" 6
We still have
FAIL: g++.dg/ext/mv1.C -std=gnu++11 (test for excess errors)
FAIL: g++.dg/ext/mv1.C -std=gnu++98 (test for excess errors)
FAIL: g++.dg/ext/pr57548.C -std=c++11 (test for excess errors)
FAIL: g++.dg/ext/pr57548.C -std=c++98 (test for excess errors)
/export/gnu/import/git/gcc/gcc/testsuite/g++.dg/ext/pr57548.C: In
function '<built-in>':^M
/export/gnu/import/git/gcc/gcc/testsuite/g++.dg/ext/pr57548.C:23:15:
error: Parameter to builtin not valid: bonnell^M
They should be fixed by Allan's patch.
Sorry for that.
--
H.J.
--
Index: ChangeLog
===================================================================
--- ChangeLog (revision 206179)
+++ ChangeLog (working copy)
@@ -1,3 +1,8 @@
+2013-12-23 H.J. Lu <hongjiu...@intel.com>
+
+ * config/i386/i386.c (processor_target_table): Move Bonnell and
+ Silvermont entries before generic.
+
2013-12-23 Bingfeng Mei <b...@broadcom.com>
PR middle-end/59569
Index: config/i386/i386.c
===================================================================
--- config/i386/i386.c (revision 206179)
+++ config/i386/i386.c (working copy)
@@ -2397,12 +2397,16 @@ static const struct ptt processor_target
{&nocona_cost, 0, 0, 0, 0, 0},
/* Core 2 */
{&core_cost, 16, 10, 16, 10, 16},
- /* Core i7 */
+ /* Nehalem */
{&core_cost, 16, 10, 16, 10, 16},
- /* Core i7 avx */
+ /* Sandy Bridge */
{&core_cost, 16, 10, 16, 10, 16},
- /* Core avx2 */
+ /* Haswell */
{&core_cost, 16, 10, 16, 10, 16},
+ /* Bonnell */
+ {&atom_cost, 16, 15, 16, 7, 16},
+ /* Silvermont */
+ {&slm_cost, 16, 15, 16, 7, 16},
{&generic_cost, 16, 10, 16, 10, 16},
{&amdfam10_cost, 32, 24, 32, 7, 32},
{&bdver1_cost, 16, 10, 16, 7, 11},
@@ -2410,9 +2414,7 @@ static const struct ptt processor_target
{&bdver3_cost, 16, 10, 16, 7, 11},
{&bdver4_cost, 16, 10, 16, 7, 11},
{&btver1_cost, 16, 10, 16, 7, 11},
- {&btver2_cost, 16, 10, 16, 7, 11},
- {&atom_cost, 16, 15, 16, 7, 16},
- {&slm_cost, 16, 15, 16, 7, 16}
+ {&btver2_cost, 16, 10, 16, 7, 11}
};
static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
