Hi,
This patch implements support for crypto pmull.64.
Tested on aarch64-none-elf. OK for trunk?
Thanks,
Tejas.
2013-12-06 Tejas Belagod <tejas.bela...@arm.com>
gcc/
* config/aarch64/aarch64-builtins.c: Define builtin types for poly64_t
poly128_t.
* aarch64/aarch64-simd-builtins.def: Update builtins table.
* config/aarch64/aarch64-simd.md (aarch64_crypto_pmulldi,
aarch64_crypto_pmullv2di): New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Update table for
poly64x2_t mangler.
* config/aarch64/arm_neon.h (poly64x2_t, poly64_t, poly128_t): Define.
(vmull_p64, vmull_high_p64): New.
* config/aarch64/iterators.md (UNSPEC_PMULL<2>): New.
testsuite/
* gcc.target/aarch64/pmull.c: New.diff --git a/gcc/config/aarch64/aarch64-builtins.c
b/gcc/config/aarch64/aarch64-builtins.c
index f4d23e7..748206f 100644
--- a/gcc/config/aarch64/aarch64-builtins.c
+++ b/gcc/config/aarch64/aarch64-builtins.c
@@ -487,6 +487,10 @@ aarch64_init_simd_builtins (void)
make_signed_type (GET_MODE_PRECISION (QImode));
tree aarch64_simd_polyHI_type_node =
make_signed_type (GET_MODE_PRECISION (HImode));
+ tree aarch64_simd_polyDI_type_node =
+ make_unsigned_type (GET_MODE_PRECISION (DImode));
+ tree aarch64_simd_polyTI_type_node =
+ make_unsigned_type (GET_MODE_PRECISION (TImode));
/* Scalar type nodes. */
tree aarch64_simd_intQI_type_node = aarch64_build_type (QImode, false);
@@ -526,6 +530,10 @@ aarch64_init_simd_builtins (void)
"__builtin_aarch64_simd_poly8");
(*lang_hooks.types.register_builtin_type) (aarch64_simd_polyHI_type_node,
"__builtin_aarch64_simd_poly16");
+ (*lang_hooks.types.register_builtin_type) (aarch64_simd_polyDI_type_node,
+ "__builtin_aarch64_simd_poly64");
+ (*lang_hooks.types.register_builtin_type) (aarch64_simd_polyTI_type_node,
+ "__builtin_aarch64_simd_poly128");
(*lang_hooks.types.register_builtin_type) (aarch64_simd_intTI_type_node,
"__builtin_aarch64_simd_ti");
(*lang_hooks.types.register_builtin_type) (aarch64_simd_intEI_type_node,
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def
b/gcc/config/aarch64/aarch64-simd-builtins.def
index dd21d9c..ec010f3 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -381,3 +381,7 @@
VAR1 (TERNOP, crypto_sha256h2, 0, v4si)
VAR1 (BINOP, crypto_sha256su0, 0, v4si)
VAR1 (TERNOP, crypto_sha256su1, 0, v4si)
+
+ /* Implemented by aarch64_crypto_pmull<mode>. */
+ VAR1 (BINOP, crypto_pmull, 0, di)
+ VAR1 (BINOP, crypto_pmull, 0, v2di)
diff --git a/gcc/config/aarch64/aarch64-simd.md
b/gcc/config/aarch64/aarch64-simd.md
index 5bcada2..6d3d70e 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -4173,3 +4173,25 @@
"sha256su1\\t%0.4s, %2.4s, %3.4s"
[(set_attr "type" "crypto_sha256_slow")]
)
+
+;; pmull
+
+(define_insn "aarch64_crypto_pmulldi"
+ [(set (match_operand:TI 0 "register_operand" "=w")
+ (unspec:TI [(match_operand:DI 1 "register_operand" "w")
+ (match_operand:DI 2 "register_operand" "w")]
+ UNSPEC_PMULL))]
+ "TARGET_SIMD && TARGET_CRYPTO"
+ "pmull\\t%0.1q, %1.1d, %2.1d"
+ [(set_attr "type" "neon_mul_d_long")]
+)
+
+(define_insn "aarch64_crypto_pmullv2di"
+ [(set (match_operand:TI 0 "register_operand" "=w")
+ (unspec:TI [(match_operand:V2DI 1 "register_operand" "w")
+ (match_operand:V2DI 2 "register_operand" "w")]
+ UNSPEC_PMULL2))]
+ "TARGET_SIMD && TARGET_CRYPTO"
+ "pmull2\\t%0.1q, %1.2d, %2.2d"
+ [(set_attr "type" "neon_mul_d_long")]
+)
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index c85947a..963bd2e 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -6370,6 +6370,7 @@ static aarch64_simd_mangle_map_entry
aarch64_simd_mangle_map[] = {
{ V2DFmode, "__builtin_aarch64_simd_df", "13__Float64x2_t" },
{ V16QImode, "__builtin_aarch64_simd_poly8", "12__Poly8x16_t" },
{ V8HImode, "__builtin_aarch64_simd_poly16", "12__Poly16x8_t" },
+ { V2DImode, "__builtin_aarch64_simd_poly64", "12__Poly64x2_t" },
{ VOIDmode, NULL, NULL }
};
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index d038e37..509b1a7 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -75,6 +75,8 @@ typedef __builtin_aarch64_simd_poly8 poly8x16_t
__attribute__ ((__vector_size__ (16)));
typedef __builtin_aarch64_simd_poly16 poly16x8_t
__attribute__ ((__vector_size__ (16)));
+typedef __builtin_aarch64_simd_poly64 poly64x2_t
+ __attribute__ ((__vector_size__ (16)));
typedef __builtin_aarch64_simd_uqi uint8x16_t
__attribute__ ((__vector_size__ (16)));
typedef __builtin_aarch64_simd_uhi uint16x8_t
@@ -88,6 +90,8 @@ typedef float float32_t;
typedef double float64_t;
typedef __builtin_aarch64_simd_poly8 poly8_t;
typedef __builtin_aarch64_simd_poly16 poly16_t;
+typedef __builtin_aarch64_simd_poly64 poly64_t;
+typedef __builtin_aarch64_simd_poly128 poly128_t;
typedef struct int8x8x2_t
{
@@ -23254,6 +23258,20 @@ vsha256su1q_u32 (uint32x4_t tw0_3, uint32x4_t w8_11,
uint32x4_t w12_15)
((int32x4_t) tw0_3, (int32x4_t) w8_11, (int32x4_t) w12_15);
}
+static __inline poly128_t
+vmull_p64 (poly64_t a, poly64_t b)
+{
+ return
+ (poly128_t) __builtin_aarch64_crypto_pmulldi ((int64x1_t)a, (int64x1_t)b);
+}
+
+static __inline poly128_t
+vmull_high_p64 (poly64x2_t a, poly64x2_t b)
+{
+ return
+ (poly128_t) __builtin_aarch64_crypto_pmullv2di ((int64x2_t)a,
(int64x2_t)b);
+}
+
#endif
/* vshl */
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index ae94e5a..2f4864c 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -277,6 +277,8 @@
UNSPEC_SHA256H2 ; Used in aarch64-simd.md.
UNSPEC_SHA256SU0 ; Used in aarch64-simd.md.
UNSPEC_SHA256SU1 ; Used in aarch64-simd.md.
+ UNSPEC_PMULL ; Used in aarch64-simd.md.
+ UNSPEC_PMULL2 ; Used in aarch64-simd.md.
])
;; -------------------------------------------------------------------
diff --git a/gcc/testsuite/gcc.target/aarch64/pmull.c
b/gcc/testsuite/gcc.target/aarch64/pmull.c
new file mode 100644
index 0000000..55079c3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pmull.c
@@ -0,0 +1,23 @@
+
+/* { dg-do compile } */
+/* { dg-options "-march=armv8-a+crypto" } */
+
+#include "arm_neon.h"
+
+poly128_t
+test_vmull_p64 (poly64_t a, poly64_t b)
+{
+ return vmull_p64 (a, b);
+}
+
+/* { dg-final { scan-assembler "pmull\\tv" } } */
+
+poly128_t
+test_vmull_high_p64 (poly64x2_t a, poly64x2_t b)
+{
+ return vmull_high_p64 (a, b);
+}
+
+/* { dg-final { scan-assembler "pmull2\\tv" } } */
+
+/* { dg-final { cleanup-saved-temps } } */
