On 26/11/13 10:07, Charles Baylis wrote: > Updated version. Only build tested. > > PR target/59142 > gcc/ > * arm/predicates.md (arm_hard_general_register_operand): New > predicate. > (vfp_hard_register_operand): Likewise. > * config/arm/arm-ldmstm.ml: Use > arm_hard_general_register_operand for all patterns. > * config/arm/ldmstm.md: Regenerate. > * gcc/config/arm/arm.md: (vfp_pop_multiple_with_writeback) Use > vfp_hard_register_operand. >
Watch out for over-long lines (79 column limit). > On 25 November 2013 14:54, Richard Earnshaw <rearn...@arm.com> wrote: >> You should delete the predicate arm_hard_register_operand if it's now >> no-longer being used. Don't forget the ChangeLog entry for that as well. > > I didn't change uses that aren't inside a define_insn, so the old > predicate is still used for now. > Grep-ing the sources doesn't show any other obvious uses outside of define_insn; so what's left? I've just spotted another problem (that was always there): > @@ -42,15 +42,15 @@ > > (define_insn "*thumb_ldm4_ia" > [(match_parallel 0 "load_multiple_operation" > - [(set (match_operand:SI 1 "arm_hard_register_operand" "") > + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") > (mem:SI (match_operand:SI 5 "s_register_operand" "l"))) > - (set (match_operand:SI 2 "arm_hard_register_operand" "") > + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") > (mem:SI (plus:SI (match_dup 5) > (const_int 4)))) > - (set (match_operand:SI 3 "arm_hard_register_operand" "") > + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") > (mem:SI (plus:SI (match_dup 5) > (const_int 8)))) > - (set (match_operand:SI 4 "arm_hard_register_operand" "") > + (set (match_operand:SI 4 "arm_hard_general_register_operand" "") > (mem:SI (plus:SI (match_dup 5) > (const_int 12))))])] > "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" This, and other thumb1 patterns should be stricter than this, since the T1 LDM/STM patterns only support low regs. I think these need changing to low_register_operand. R.
