diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c
old mode 100644
new mode 100755
index a4a1f40..0b8af3f
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@@ -646,6 +646,11 @@ const char *host_detect_local_cpu (int argc, const char **argv)
 	  /* Atom.  */
 	  cpu = "atom";
 	  break;
+	case 0x37:
+	case 0x4d:
+	  /* Silvermont.  */
+	  cpu = "slm";
+	  break;
 	case 0x0f:
 	  /* Merom.  */
 	case 0x17:
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
old mode 100644
new mode 100755
index 459281e..4bc9ebf
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -3137,8 +3137,8 @@ ix86_option_override_internal (bool main_args_p,
 	| PTA_SSSE3 | PTA_CX16 | PTA_MOVBE | PTA_FXSR},
       {"slm", PROCESSOR_SLM, CPU_SLM,
 	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
-	| PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_MOVBE
-	| PTA_FXSR},
+	| PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_AES
+	| PTA_PCLMUL | PTA_RDRND | PTA_MOVBE | PTA_FXSR},
       {"geode", PROCESSOR_GEODE, CPU_GEODE,
 	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE | PTA_PRFCHW},
       {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
old mode 100644
new mode 100755
index 6adfc98..7048b0b
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -14535,7 +14535,7 @@ instruction set support.
 
 @item slm
 Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
-SSE4.1, SSE4.2 and POPCNT instruction set support.
+SSE4.1, SSE4.2, POPCNT, AES, PCLMUL and RDRND instruction set support.
 
 @item k6
 AMD K6 CPU with MMX instruction set support.
diff --git a/libgcc/config/i386/cpuinfo.c b/libgcc/config/i386/cpuinfo.c
old mode 100644
new mode 100755
index 1c744f1..1a891e0
--- a/libgcc/config/i386/cpuinfo.c
+++ b/libgcc/config/i386/cpuinfo.c
@@ -170,6 +170,11 @@ get_intel_cpu (unsigned int family, unsigned int model, unsigned int brand_id)
 	      /* Atom.  */
 	      __cpu_model.__cpu_type = INTEL_ATOM;
 	      break;
+	    case 0x37:
+	    case 0x4d:
+	      /* Silvermont.  */
+	      __cpu_model.__cpu_type = INTEL_SLM;
+	      break;
 	    case 0x1a:
 	    case 0x1e:
 	    case 0x1f: