Hi all,
This patch adds the rtx costs table for the Cortex-A9 core.
An arm-none-eabi regression run tuned for A9 succeeded.
This costs tabled showed a slight improvement on some popular benchmarks and no
performance regressions on others against the old way of doing rtx costs.
Ok for trunk?
Thanks,
Kyrill
[gcc/]
2013-10-17 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
* config/arm/arm.c (cortexa9_extra_costs): New table.
(arm_cortex_a9_tune): Use cortexa9_extra_costs.diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 49636d2..8a522b6 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -1152,6 +1152,108 @@ const struct cpu_cost_table cortexa12_extra_costs =
}
};
+
+const struct cpu_cost_table cortexa9_extra_costs =
+{
+ /* ALU */
+ {
+ 0, /* Arith. */
+ 0, /* Logical. */
+ 0, /* Shift. */
+ COSTS_N_INSNS (1), /* Shift_reg. */
+ COSTS_N_INSNS (1), /* Arith_shift. */
+ COSTS_N_INSNS (2), /* Arith_shift_reg. */
+ 0, /* Log_shift. */
+ COSTS_N_INSNS (1), /* Log_shift_reg. */
+ COSTS_N_INSNS (1), /* Extend. */
+ COSTS_N_INSNS (2), /* Extend_arith. */
+ COSTS_N_INSNS (1), /* Bfi. */
+ COSTS_N_INSNS (1), /* Bfx. */
+ 0, /* Clz. */
+ 0, /* non_exec. */
+ true /* non_exec_costs_exec. */
+ },
+ {
+ /* MULT SImode */
+ {
+ COSTS_N_INSNS (3), /* Simple. */
+ COSTS_N_INSNS (3), /* Flag_setting. */
+ COSTS_N_INSNS (4), /* Extend. */
+ COSTS_N_INSNS (3), /* Add. */
+ COSTS_N_INSNS (4), /* Extend_add. */
+ COSTS_N_INSNS (30) /* Idiv. No HW div on Cortex A9. */
+ },
+ /* MULT DImode */
+ {
+ 0, /* Simple (N/A). */
+ 0, /* Flag_setting (N/A). */
+ 0, /* Extend (N/A). */
+ 0, /* Add (N/A). */
+ 0, /* Extend_add (N/A). */
+ 0 /* Idiv (N/A). */
+ }
+ },
+ /* LD/ST */
+ {
+ COSTS_N_INSNS (2), /* Load. */
+ COSTS_N_INSNS (2), /* Load_sign_extend. */
+ COSTS_N_INSNS (2), /* Ldrd. */
+ COSTS_N_INSNS (2), /* Ldm_1st. */
+ 1, /* Ldm_regs_per_insn_1st. */
+ 2, /* Ldm_regs_per_insn_subsequent. */
+ COSTS_N_INSNS (5), /* Loadf. */
+ COSTS_N_INSNS (5), /* Loadd. */
+ COSTS_N_INSNS (1), /* Load_unaligned. */
+ COSTS_N_INSNS (2), /* Store. */
+ COSTS_N_INSNS (2), /* Strd. */
+ COSTS_N_INSNS (2), /* Stm_1st. */
+ 1, /* Stm_regs_per_insn_1st. */
+ 2, /* Stm_regs_per_insn_subsequent. */
+ COSTS_N_INSNS (1), /* Storef. */
+ COSTS_N_INSNS (1), /* Stored. */
+ COSTS_N_INSNS (1) /* Store_unaligned. */
+ },
+ {
+ /* FP SFmode */
+ {
+ COSTS_N_INSNS (14), /* Div. */
+ COSTS_N_INSNS (4), /* Mult. */
+ COSTS_N_INSNS (7), /* Mult_addsub. */
+ COSTS_N_INSNS (30), /* Fma. */
+ COSTS_N_INSNS (3), /* Addsub. */
+ COSTS_N_INSNS (1), /* Fpconst. */
+ COSTS_N_INSNS (1), /* Neg. */
+ COSTS_N_INSNS (3), /* Compare. */
+ COSTS_N_INSNS (3), /* Widen. */
+ COSTS_N_INSNS (3), /* Narrow. */
+ COSTS_N_INSNS (3), /* Toint. */
+ COSTS_N_INSNS (3), /* Fromint. */
+ COSTS_N_INSNS (3) /* Roundint. */
+ },
+ /* FP DFmode */
+ {
+ COSTS_N_INSNS (24), /* Div. */
+ COSTS_N_INSNS (5), /* Mult. */
+ COSTS_N_INSNS (8), /* Mult_addsub. */
+ COSTS_N_INSNS (30), /* Fma. */
+ COSTS_N_INSNS (3), /* Addsub. */
+ COSTS_N_INSNS (1), /* Fpconst. */
+ COSTS_N_INSNS (1), /* Neg. */
+ COSTS_N_INSNS (3), /* Compare. */
+ COSTS_N_INSNS (3), /* Widen. */
+ COSTS_N_INSNS (3), /* Narrow. */
+ COSTS_N_INSNS (3), /* Toint. */
+ COSTS_N_INSNS (3), /* Fromint. */
+ COSTS_N_INSNS (3) /* Roundint. */
+ }
+ },
+ /* Vector */
+ {
+ COSTS_N_INSNS (1) /* Alu. */
+ }
+};
+
+
const struct cpu_cost_table cortexa15_extra_costs =
{
/* ALU */
@@ -1554,7 +1656,7 @@ const struct tune_params arm_cortex_a5_tune =
const struct tune_params arm_cortex_a9_tune =
{
arm_9e_rtx_costs,
- NULL,
+ &cortexa9_extra_costs,
cortex_a9_sched_adjust_cost,
1, /* Constant limit. */
5, /* Max cond insns. */
