On 27/08/13 12:10, Richard Biener wrote: > What's this for and what's the desired semantics? I don't like having > extra tree codes for this. Is this for a specific instruction set > feature?
The background is to support the conditional compare instructions in ARM (more effectively) and AArch64 at all. The current method used in ARM is to expand into a series of store-flag instructions and then hope that combine can optimize them away (though that fails far too often, particularly when the first instruction in the sequence is combined into another pattern). To make it work at all the compiler has to lie about the costs of various store-flag type operations which overall risks producing worse code and means we also have to support many more complex multi-instruction patterns than is desirable. I really don't want to go down the same route for AArch64. The idea behind all this is to capture potential conditional compare operations early enough in the mid end that we can keep track of them until RTL expand time and then to emit the correct logic on all targets depending on what is the best thing for that target. The current method of lowering into store-flag sequences doesn't really cut it. R.
