http://gcc.gnu.org/viewcvs/gcc?view=revision&revision=201121
Applied this obvious improvement of the sequence to load one byte from address
space memx (provided no ELPM is need).
The old sequence was
SBRC msb
LD reg, Z ; read from RAM
SBRS msp
LPM reg, Z ; read from flash
and the new one is
LPM reg, Z ; read from flash
SBRC msb
LD reg, Z ; read from RAM
This is legal because LPM never causes side effects.
Johann
* config/avr/avr.c (avr_out_xload): No SBIS around LPM so that
instruction sequence is 1 byte shorter.
Index: config/avr/avr.c
===================================================================
--- config/avr/avr.c (revision 201119)
+++ config/avr/avr.c (working copy)
@@ -3079,14 +3079,10 @@ avr_out_xload (rtx insn ATTRIBUTE_UNUSED
xop[2] = lpm_addr_reg_rtx;
xop[3] = AVR_HAVE_LPMX ? op[0] : lpm_reg_rtx;
- if (plen)
- *plen = 0;
+ avr_asm_len (AVR_HAVE_LPMX ? "lpm %3,%a2" : "lpm", xop, plen, -1);
avr_asm_len ("sbrc %1,7" CR_TAB
- "ld %3,%a2" CR_TAB
- "sbrs %1,7", xop, plen, 3);
-
- avr_asm_len (AVR_HAVE_LPMX ? "lpm %3,%a2" : "lpm", xop, plen, 1);
+ "ld %3,%a2", xop, plen, 2);
if (REGNO (xop[0]) != REGNO (xop[3]))
avr_asm_len ("mov %0,%3", xop, plen, 1);
