On Mon, Jul 08, 2013 at 01:03:38PM +0200, Uros Bizjak wrote:
> Hello!
>
> > the attached patch adds F0_REGNUM ... F15_REGNUM and uses these
> > throughout the s390.c file. The FPR numbering in the s390 backend is
> > not obvious and this hopefully makes it easier to get right for me.
>
> Index: gcc/config/s390/s390.h
> ===================================================================
> *** gcc/config/s390/s390.h.orig
> --- gcc/config/s390/s390.h
> *************** enum reg_class
> *** 477,482 ****
> --- 477,499 ----
> { 0xffffffff, 0x0000003f }, /* ALL_REGS */ \
> }
>
> + #define F0_REGNUM 16
> + #define F1_REGNUM 20
> + #define F2_REGNUM 17
> + #define F3_REGNUM 21
> + #define F4_REGNUM 18
> + #define F5_REGNUM 22
> + #define F6_REGNUM 19
> + #define F7_REGNUM 23
> + #define F8_REGNUM 24
> + #define F9_REGNUM 25
> + #define F10_REGNUM 26
> + #define F11_REGNUM 27
> + #define F12_REGNUM 28
> + #define F13_REGNUM 29
> + #define F14_REGNUM 30
> + #define F15_REGNUM 31
>
> You can add these as define_constant in s390.md (see for example
> i386.md). There is already definition of FPR0_REGNUM and FPR2_REGNUM,
> which is now incostistent (18) with your new definitions (17).
Thanks. Now it probably became apparent that I need a vehicle to help
me with the S/390 FPR numbering.
The existing constant (FPR2_REGNUM) was wrong as well as my new macros
(>F8).
I'll commit the attached patch after successful testing.
Bye,
-Andreas-
2013-07-08 Andreas Krebbel <andreas.kreb...@de.ibm.com>
* config/s390/s390.c: Replace F*_REGNUM with FPR*_REGNUM.
* config/s390/s390.h: Remove F*_REGNUM macro definitions.
* config/s390/s390.md: Define FPR*_REGNUM constants.
Fix FPR2_REGNUM constant (18 -> 17).
("*trunc<BFP:mode><DFP_ALL:mode>2")
("*trunc<DFP_ALL:mode><BFP:mode>2")
("trunc<BFP:mode><DFP_ALL:mode>2")
("trunc<DFP_ALL:mode><BFP:mode>2")
("*extend<BFP:mode><DFP_ALL:mode>2")
("*extend<DFP_ALL:mode><BFP:mode>2")
("extend<BFP:mode><DFP_ALL:mode>2")
("extend<DFP_ALL:mode><BFP:mode>2"): Replace FPR2_REGNUM with
FPR4_REGNUM.
---
gcc/config/s390/s390.c | 74 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
gcc/config/s390/s390.h | 17 -----------
gcc/config/s390/s390.md | 40 !!!!!!!!!!!!!!!!!!!!!!!!!
3 files changed, 17 deletions(-), 114 modifications(!)
Index: gcc/config/s390/s390.c
===================================================================
*** gcc/config/s390/s390.c.orig
--- gcc/config/s390/s390.c
*************** struct GTY (()) s390_frame_layout
*** 333,341 ****
/* Bits standing for floating point registers. Set, if the
respective register has to be saved. Starting with reg 16 (f0)
at the rightmost bit.
! Bit 15 - 8 7 6 5 4 3 2 1 0
! fpr 15 - 8 7 5 3 1 6 4 2 0
! reg 31 - 24 23 22 21 20 19 18 17 16 */
unsigned int fpr_bitmap;
/* Number of floating point registers f8-f15 which must be saved. */
--- 333,341 ----
/* Bits standing for floating point registers. Set, if the
respective register has to be saved. Starting with reg 16 (f0)
at the rightmost bit.
! Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
! fpr 15 13 11 9 14 12 10 8 7 5 3 1 6 4 2 0
! reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 */
unsigned int fpr_bitmap;
/* Number of floating point registers f8-f15 which must be saved. */
*************** struct GTY(()) machine_function
*** 380,388 ****
#define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot -
\
cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
#define cfun_set_fpr_save(REGNO) (cfun->machine->frame_layout.fpr_bitmap |=
\
! (1 << (REGNO - F0_REGNUM)))
#define cfun_fpr_save_p(REGNO) (!!(cfun->machine->frame_layout.fpr_bitmap &
\
! (1 << (REGNO - F0_REGNUM))))
/* Number of GPRs and FPRs used for argument passing. */
#define GP_ARG_NUM_REG 5
--- 380,388 ----
#define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot -
\
cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
#define cfun_set_fpr_save(REGNO) (cfun->machine->frame_layout.fpr_bitmap |=
\
! (1 << (REGNO - FPR0_REGNUM)))
#define cfun_fpr_save_p(REGNO) (!!(cfun->machine->frame_layout.fpr_bitmap &
\
! (1 << (REGNO - FPR0_REGNUM))))
/* Number of GPRs and FPRs used for argument passing. */
#define GP_ARG_NUM_REG 5
*************** s390_frame_area (int *area_bottom, int *
*** 7472,7483 ****
if (!TARGET_64BIT)
{
! if (cfun_fpr_save_p (F4_REGNUM))
{
b = MIN (b, cfun_frame_layout.f4_offset);
t = MAX (t, cfun_frame_layout.f4_offset + 8);
}
! if (cfun_fpr_save_p (F6_REGNUM))
{
b = MIN (b, cfun_frame_layout.f4_offset + 8);
t = MAX (t, cfun_frame_layout.f4_offset + 16);
--- 7472,7483 ----
if (!TARGET_64BIT)
{
! if (cfun_fpr_save_p (FPR4_REGNUM))
{
b = MIN (b, cfun_frame_layout.f4_offset);
t = MAX (t, cfun_frame_layout.f4_offset + 8);
}
! if (cfun_fpr_save_p (FPR6_REGNUM))
{
b = MIN (b, cfun_frame_layout.f4_offset + 8);
t = MAX (t, cfun_frame_layout.f4_offset + 16);
*************** s390_register_info (int clobbered_regs[]
*** 7509,7515 ****
cfun_frame_layout.fpr_bitmap = 0;
cfun_frame_layout.high_fprs = 0;
if (TARGET_64BIT)
! for (i = F8_REGNUM; i <= F15_REGNUM; i++)
/* During reload we have to use the df_regs_ever_live infos
since reload is marking FPRs used as spill slots there as
live before actually making the code changes. Without
--- 7509,7515 ----
cfun_frame_layout.fpr_bitmap = 0;
cfun_frame_layout.high_fprs = 0;
if (TARGET_64BIT)
! for (i = FPR8_REGNUM; i <= FPR15_REGNUM; i++)
/* During reload we have to use the df_regs_ever_live infos
since reload is marking FPRs used as spill slots there as
live before actually making the code changes. Without
*************** s390_register_info (int clobbered_regs[]
*** 7648,7663 ****
min_fpr = 0;
for (i = min_fpr; i < max_fpr; i++)
! cfun_set_fpr_save (i + F0_REGNUM);
}
}
if (!TARGET_64BIT)
{
! if (df_regs_ever_live_p (F4_REGNUM) && !global_regs[F4_REGNUM])
! cfun_set_fpr_save (F4_REGNUM);
! if (df_regs_ever_live_p (F6_REGNUM) && !global_regs[F6_REGNUM])
! cfun_set_fpr_save (F6_REGNUM);
}
}
--- 7648,7663 ----
min_fpr = 0;
for (i = min_fpr; i < max_fpr; i++)
! cfun_set_fpr_save (i + FPR0_REGNUM);
}
}
if (!TARGET_64BIT)
{
! if (df_regs_ever_live_p (FPR4_REGNUM) && !global_regs[FPR4_REGNUM])
! cfun_set_fpr_save (FPR4_REGNUM);
! if (df_regs_ever_live_p (FPR6_REGNUM) && !global_regs[FPR6_REGNUM])
! cfun_set_fpr_save (FPR6_REGNUM);
}
}
*************** s390_frame_info (void)
*** 7694,7706 ****
{
cfun_frame_layout.f4_offset
= (cfun_frame_layout.gprs_offset
! - 8 * (cfun_fpr_save_p (F4_REGNUM)
! + cfun_fpr_save_p (F6_REGNUM)));
cfun_frame_layout.f0_offset
= (cfun_frame_layout.f4_offset
! - 8 * (cfun_fpr_save_p (F0_REGNUM)
! + cfun_fpr_save_p (F2_REGNUM)));
}
else
{
--- 7694,7706 ----
{
cfun_frame_layout.f4_offset
= (cfun_frame_layout.gprs_offset
! - 8 * (cfun_fpr_save_p (FPR4_REGNUM)
! + cfun_fpr_save_p (FPR6_REGNUM)));
cfun_frame_layout.f0_offset
= (cfun_frame_layout.f4_offset
! - 8 * (cfun_fpr_save_p (FPR0_REGNUM)
! + cfun_fpr_save_p (FPR2_REGNUM)));
}
else
{
*************** s390_frame_info (void)
*** 7709,7734 ****
cfun_frame_layout.f0_offset
= ((cfun_frame_layout.gprs_offset
& ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
! - 8 * (cfun_fpr_save_p (F0_REGNUM)
! + cfun_fpr_save_p (F2_REGNUM)));
cfun_frame_layout.f4_offset
= (cfun_frame_layout.f0_offset
! - 8 * (cfun_fpr_save_p (F4_REGNUM)
! + cfun_fpr_save_p (F6_REGNUM)));
}
}
else /* no backchain */
{
cfun_frame_layout.f4_offset
= (STACK_POINTER_OFFSET
! - 8 * (cfun_fpr_save_p (F4_REGNUM)
! + cfun_fpr_save_p (F6_REGNUM)));
cfun_frame_layout.f0_offset
= (cfun_frame_layout.f4_offset
! - 8 * (cfun_fpr_save_p (F0_REGNUM)
! + cfun_fpr_save_p (F2_REGNUM)));
cfun_frame_layout.gprs_offset
= cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
--- 7709,7734 ----
cfun_frame_layout.f0_offset
= ((cfun_frame_layout.gprs_offset
& ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
! - 8 * (cfun_fpr_save_p (FPR0_REGNUM)
! + cfun_fpr_save_p (FPR2_REGNUM)));
cfun_frame_layout.f4_offset
= (cfun_frame_layout.f0_offset
! - 8 * (cfun_fpr_save_p (FPR4_REGNUM)
! + cfun_fpr_save_p (FPR6_REGNUM)));
}
}
else /* no backchain */
{
cfun_frame_layout.f4_offset
= (STACK_POINTER_OFFSET
! - 8 * (cfun_fpr_save_p (FPR4_REGNUM)
! + cfun_fpr_save_p (FPR6_REGNUM)));
cfun_frame_layout.f0_offset
= (cfun_frame_layout.f4_offset
! - 8 * (cfun_fpr_save_p (FPR0_REGNUM)
! + cfun_fpr_save_p (FPR2_REGNUM)));
cfun_frame_layout.gprs_offset
= cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
*************** s390_frame_info (void)
*** 7760,7766 ****
cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
! for (i = F0_REGNUM; i <= F7_REGNUM; i++)
if (cfun_fpr_save_p (i))
cfun_frame_layout.frame_size += 8;
--- 7760,7766 ----
cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
! for (i = FPR0_REGNUM; i <= FPR7_REGNUM; i++)
if (cfun_fpr_save_p (i))
cfun_frame_layout.frame_size += 8;
*************** s390_emit_prologue (void)
*** 8466,8472 ****
offset = cfun_frame_layout.f0_offset;
/* Save f0 and f2. */
! for (i = F0_REGNUM; i <= F0_REGNUM + 1; i++)
{
if (cfun_fpr_save_p (i))
{
--- 8466,8472 ----
offset = cfun_frame_layout.f0_offset;
/* Save f0 and f2. */
! for (i = FPR0_REGNUM; i <= FPR0_REGNUM + 1; i++)
{
if (cfun_fpr_save_p (i))
{
*************** s390_emit_prologue (void)
*** 8479,8485 ****
/* Save f4 and f6. */
offset = cfun_frame_layout.f4_offset;
! for (i = F4_REGNUM; i <= F4_REGNUM + 1; i++)
{
if (cfun_fpr_save_p (i))
{
--- 8479,8485 ----
/* Save f4 and f6. */
offset = cfun_frame_layout.f4_offset;
! for (i = FPR4_REGNUM; i <= FPR4_REGNUM + 1; i++)
{
if (cfun_fpr_save_p (i))
{
*************** s390_emit_prologue (void)
*** 8502,8508 ****
offset = (cfun_frame_layout.f8_offset
+ (cfun_frame_layout.high_fprs - 1) * 8);
! for (i = F15_REGNUM; i >= F8_REGNUM && offset >= 0; i--)
if (cfun_fpr_save_p (i))
{
insn = save_fpr (stack_pointer_rtx, offset, i);
--- 8502,8508 ----
offset = (cfun_frame_layout.f8_offset
+ (cfun_frame_layout.high_fprs - 1) * 8);
! for (i = FPR15_REGNUM; i >= FPR8_REGNUM && offset >= 0; i--)
if (cfun_fpr_save_p (i))
{
insn = save_fpr (stack_pointer_rtx, offset, i);
*************** s390_emit_prologue (void)
*** 8515,8521 ****
}
if (!TARGET_PACKED_STACK)
! next_fpr = cfun_save_high_fprs_p ? F15_REGNUM : 0;
if (flag_stack_usage_info)
current_function_static_stack_size = cfun_frame_layout.frame_size;
--- 8515,8521 ----
}
if (!TARGET_PACKED_STACK)
! next_fpr = cfun_save_high_fprs_p ? FPR15_REGNUM : 0;
if (flag_stack_usage_info)
current_function_static_stack_size = cfun_frame_layout.frame_size;
*************** s390_emit_prologue (void)
*** 8660,8666 ****
offset = 0;
! for (i = F8_REGNUM; i <= next_fpr; i++)
if (cfun_fpr_save_p (i))
{
rtx addr = plus_constant (Pmode, stack_pointer_rtx,
--- 8660,8666 ----
offset = 0;
! for (i = FPR8_REGNUM; i <= next_fpr; i++)
if (cfun_fpr_save_p (i))
{
rtx addr = plus_constant (Pmode, stack_pointer_rtx,
*************** s390_emit_epilogue (bool sibcall)
*** 8790,8796 ****
if (cfun_save_high_fprs_p)
{
next_offset = cfun_frame_layout.f8_offset;
! for (i = F8_REGNUM; i <= F15_REGNUM; i++)
{
if (cfun_fpr_save_p (i))
{
--- 8790,8796 ----
if (cfun_save_high_fprs_p)
{
next_offset = cfun_frame_layout.f8_offset;
! for (i = FPR8_REGNUM; i <= FPR15_REGNUM; i++)
{
if (cfun_fpr_save_p (i))
{
*************** s390_emit_epilogue (bool sibcall)
*** 8809,8815 ****
{
next_offset = cfun_frame_layout.f4_offset;
/* f4, f6 */
! for (i = F4_REGNUM; i <= F4_REGNUM + 1; i++)
{
if (cfun_fpr_save_p (i))
{
--- 8809,8815 ----
{
next_offset = cfun_frame_layout.f4_offset;
/* f4, f6 */
! for (i = FPR4_REGNUM; i <= FPR4_REGNUM + 1; i++)
{
if (cfun_fpr_save_p (i))
{
*************** s390_conditional_register_usage (void)
*** 10518,10535 ****
}
if (TARGET_64BIT)
{
! for (i = F8_REGNUM; i <= F15_REGNUM; i++)
call_used_regs[i] = call_really_used_regs[i] = 0;
}
else
{
! call_used_regs[F4_REGNUM] = call_really_used_regs[F4_REGNUM] = 0;
! call_used_regs[F6_REGNUM] = call_really_used_regs[F6_REGNUM] = 0;
}
if (TARGET_SOFT_FLOAT)
{
! for (i = F0_REGNUM; i <= F15_REGNUM; i++)
call_used_regs[i] = fixed_regs[i] = 1;
}
}
--- 10518,10535 ----
}
if (TARGET_64BIT)
{
! for (i = FPR8_REGNUM; i <= FPR15_REGNUM; i++)
call_used_regs[i] = call_really_used_regs[i] = 0;
}
else
{
! call_used_regs[FPR4_REGNUM] = call_really_used_regs[FPR4_REGNUM] = 0;
! call_used_regs[FPR6_REGNUM] = call_really_used_regs[FPR6_REGNUM] = 0;
}
if (TARGET_SOFT_FLOAT)
{
! for (i = FPR0_REGNUM; i <= FPR15_REGNUM; i++)
call_used_regs[i] = fixed_regs[i] = 1;
}
}
Index: gcc/config/s390/s390.h
===================================================================
*** gcc/config/s390/s390.h.orig
--- gcc/config/s390/s390.h
*************** enum reg_class
*** 477,499 ****
{ 0xffffffff, 0x0000003f }, /* ALL_REGS */ \
}
- #define F0_REGNUM 16
- #define F1_REGNUM 20
- #define F2_REGNUM 17
- #define F3_REGNUM 21
- #define F4_REGNUM 18
- #define F5_REGNUM 22
- #define F6_REGNUM 19
- #define F7_REGNUM 23
- #define F8_REGNUM 24
- #define F9_REGNUM 25
- #define F10_REGNUM 26
- #define F11_REGNUM 27
- #define F12_REGNUM 28
- #define F13_REGNUM 29
- #define F14_REGNUM 30
- #define F15_REGNUM 31
-
/* In some case register allocation order is not enough for IRA to
generate a good code. The following macro (if defined) increases
cost of REGNO for a pseudo approximately by pseudo usage frequency
--- 477,482 ----
Index: gcc/config/s390/s390.md
===================================================================
*** gcc/config/s390/s390.md.orig
--- gcc/config/s390/s390.md
***************
*** 183,189 ****
(GPR0_REGNUM 0)
; Floating point registers.
(FPR0_REGNUM 16)
! (FPR2_REGNUM 18)
])
;;
--- 183,203 ----
(GPR0_REGNUM 0)
; Floating point registers.
(FPR0_REGNUM 16)
! (FPR1_REGNUM 20)
! (FPR2_REGNUM 17)
! (FPR3_REGNUM 21)
! (FPR4_REGNUM 18)
! (FPR5_REGNUM 22)
! (FPR6_REGNUM 19)
! (FPR7_REGNUM 23)
! (FPR8_REGNUM 24)
! (FPR9_REGNUM 28)
! (FPR10_REGNUM 25)
! (FPR11_REGNUM 29)
! (FPR12_REGNUM 26)
! (FPR13_REGNUM 30)
! (FPR14_REGNUM 27)
! (FPR15_REGNUM 31)
])
;;
***************
*** 4405,4411 ****
(define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
[(set (reg:DFP_ALL FPR0_REGNUM)
! (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
(use (reg:SI GPR0_REGNUM))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_DFP"
--- 4419,4425 ----
(define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
[(set (reg:DFP_ALL FPR0_REGNUM)
! (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
(use (reg:SI GPR0_REGNUM))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_DFP"
***************
*** 4413,4430 ****
(define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
[(set (reg:BFP FPR0_REGNUM)
! (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
(use (reg:SI GPR0_REGNUM))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_DFP"
"pfpo")
(define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
! [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
(set (reg:SI GPR0_REGNUM) (match_dup 2))
(parallel
[(set (reg:DFP_ALL FPR0_REGNUM)
! (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
(use (reg:SI GPR0_REGNUM))
(clobber (reg:CC CC_REGNUM))])
(set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
--- 4427,4444 ----
(define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
[(set (reg:BFP FPR0_REGNUM)
! (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
(use (reg:SI GPR0_REGNUM))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_DFP"
"pfpo")
(define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
! [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
(set (reg:SI GPR0_REGNUM) (match_dup 2))
(parallel
[(set (reg:DFP_ALL FPR0_REGNUM)
! (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
(use (reg:SI GPR0_REGNUM))
(clobber (reg:CC CC_REGNUM))])
(set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
***************
*** 4442,4452 ****
})
(define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
! [(set (reg:DFP_ALL FPR2_REGNUM)
(match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
(set (reg:SI GPR0_REGNUM) (match_dup 2))
(parallel
! [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL
FPR2_REGNUM)))
(use (reg:SI GPR0_REGNUM))
(clobber (reg:CC CC_REGNUM))])
(set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP
FPR0_REGNUM))]
--- 4456,4466 ----
})
(define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
! [(set (reg:DFP_ALL FPR4_REGNUM)
(match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
(set (reg:SI GPR0_REGNUM) (match_dup 2))
(parallel
! [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL
FPR4_REGNUM)))
(use (reg:SI GPR0_REGNUM))
(clobber (reg:CC CC_REGNUM))])
(set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP
FPR0_REGNUM))]
***************
*** 4467,4491 ****
;
(define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
! [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP
FPR2_REGNUM)))
(use (reg:SI GPR0_REGNUM))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_DFP"
"pfpo")
(define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
! [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
(use (reg:SI GPR0_REGNUM))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_DFP"
"pfpo")
(define_expand "extend<BFP:mode><DFP_ALL:mode>2"
! [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
(set (reg:SI GPR0_REGNUM) (match_dup 2))
(parallel
[(set (reg:DFP_ALL FPR0_REGNUM)
! (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
(use (reg:SI GPR0_REGNUM))
(clobber (reg:CC CC_REGNUM))])
(set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
--- 4481,4505 ----
;
(define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
! [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP
FPR4_REGNUM)))
(use (reg:SI GPR0_REGNUM))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_DFP"
"pfpo")
(define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
! [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
(use (reg:SI GPR0_REGNUM))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_DFP"
"pfpo")
(define_expand "extend<BFP:mode><DFP_ALL:mode>2"
! [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
(set (reg:SI GPR0_REGNUM) (match_dup 2))
(parallel
[(set (reg:DFP_ALL FPR0_REGNUM)
! (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
(use (reg:SI GPR0_REGNUM))
(clobber (reg:CC CC_REGNUM))])
(set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
***************
*** 4503,4513 ****
})
(define_expand "extend<DFP_ALL:mode><BFP:mode>2"
! [(set (reg:DFP_ALL FPR2_REGNUM)
(match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
(set (reg:SI GPR0_REGNUM) (match_dup 2))
(parallel
! [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
(use (reg:SI GPR0_REGNUM))
(clobber (reg:CC CC_REGNUM))])
(set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP
FPR0_REGNUM))]
--- 4517,4527 ----
})
(define_expand "extend<DFP_ALL:mode><BFP:mode>2"
! [(set (reg:DFP_ALL FPR4_REGNUM)
(match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
(set (reg:SI GPR0_REGNUM) (match_dup 2))
(parallel
! [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
(use (reg:SI GPR0_REGNUM))
(clobber (reg:CC CC_REGNUM))])
(set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP
FPR0_REGNUM))]
