On Tue, 11 Jun 2013, Steve Ellcey wrote:
> Sorry, it should have been 'main(void) {return 0; }. Then you get (with
> the patch):
>
> j $31
> move $2,$0
>
> instead of:
>
> move $2,$0
> j $31
Hmm, something must have been missed then from the microMIPS patches as
our toolchain seems to get this case right:
.set noreorder
.set nomacro
jr $31
move $2,$0
.set macro
.set reorder
(no idea where the extraneous newline comes from, hmm). Catherine, can
you please double-check you haven't got anything outstanding yet?
> > Is it safe to assume an RTL insn whose length is 4 has only a single
> > machine instruction in the microMIPS mode? What's the difference to the
> > MIPS16 instruction set here?
>
> I think so, I don't know of any microMIPS RTL instructions whose length
> is 4 that would not be a single instruction. Maybe I should add
> Catherine in to the discussion to see if she knows differently.
I advise care here, even if we currently have no such pattern. It's easy
to miss the dependency and any such bug introduced could trigger very
rarely only. Also (unlike with the standard ISA) some otherwise ordinary
instructions can't be scheduled into a delay slot, e.g. MOVEP or
LWP/LDP/SWP/SDP.
Maciej
