> On 06/06/13 17:26, Richard Henderson wrote: > > On 06/06/2013 08:02 AM, Richard Earnshaw wrote: > >> (define_insn "add<mode>3" > >> - [(set (match_operand:FIXED 0 "s_register_operand" "=r") > >> - (plus:FIXED (match_operand:FIXED 1 "s_register_operand" > "r") > >> - (match_operand:FIXED 2 "s_register_operand" "r")))] > >> + [(set (match_operand:FIXED 0 "s_register_operand" "=r,l") > >> + (plus:FIXED (match_operand:FIXED 1 "s_register_operand" > "r,l") > >> + (match_operand:FIXED 2 "s_register_operand" > "r,l")))] > >> > >> It would probably be better to put the 'l' variant first. This > should encourage > >> register allocation to prefer low registers and that might lead > to other > >> optimizations later on. Similarly for sub<mode>3. > > > > It's also 100% required in order to make the l alternative ever > chosen. > > > > When we compute which_alternative post-reload, we'll see that r > matches > > and always choose alternative 0. If you've been examining asm > dumps of > > various test cases, in addition to your bootstrapping, you'll > have seen > > no IT predicated addition insns after this patch. > > > > > > r~ > > > > Not quite. In the cond-exec case the first alternative can be > disabled, > then only those cases that match the second set of constraints > could be > conditionalized.
In any case, I've committed the patch with the 'l' constraint going before 'r' as r199739. Thanks for the review. Kyrill
