Similar to lshr, for ashl. Okay?
2013-05-31 Segher Boessenkool <seg...@kernel.crashing.org>
gcc/
* config/rs6000/rs6000.md (ashlsi3, ashldi3_internal1,
ashldi3_internal2, ashldi3_internal3): Delete.
* config/rs6000/integer.mdm (ashl<mode>3, ashl<mode>3_imm): New.
* config/rs6000/integer.md: Regenerate.
---
gcc/config/rs6000/integer.md | 162 ++++++++++++++++++++++++++++++++++++++++++
gcc/config/rs6000/integer.mdm | 20 ++++++
gcc/config/rs6000/rs6000.md | 147 --------------------------------------
3 files changed, 182 insertions(+), 147 deletions(-)
diff --git a/gcc/config/rs6000/integer.md b/gcc/config/rs6000/integer.md
index 2be1f35..e1520bc 100644
--- a/gcc/config/rs6000/integer.md
+++ b/gcc/config/rs6000/integer.md
@@ -32,6 +32,168 @@
; slw[.], srw[.], srawi[.], sraw[.], sld[.], srd[.], sradi[.], srad[.]
+(define_insn "ashl<mode>3"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+ (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "gpc_reg_operand" "r")))]
+ ""
+ "sl<wd> %0,%1,%2"
+ [(set_attr "type" "var_shift_rotate") ; var_delayed_compare
+])
+
+(define_insn "*ashl<mode>3_dot"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+ (compare:CC
+ (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
+ (match_operand:SI 2 "gpc_reg_operand" "r,r"))
+ (const_int 0)))
+ (clobber (match_scratch:GPR 0 "=r,r"))]
+ "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
+ "@
+ sl<wd>. %0,%1,%2
+ #"
+ [(set_attr "length" "4,8")
+ (set_attr "dot" "yes,no")
+ (set_attr "type" "var_shift_rotate") ; var_delayed_compare
+])
+
+(define_split
+ [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+ (compare:CC
+ (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
+ (match_operand:SI 2 "gpc_reg_operand" ""))
+ (const_int 0)))
+ (clobber (match_scratch:GPR 0 ""))]
+ "(<MODE>mode == Pmode && rs6000_gen_cell_microcode)
+ && (reload_completed)"
+ [(set (match_dup 0)
+ (ashift:GPR (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 3)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ "")
+
+(define_insn "*ashl<mode>3_dot2"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+ (compare:CC
+ (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
+ (match_operand:SI 2 "gpc_reg_operand" "r,r"))
+ (const_int 0)))
+ (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
+ (ashift:GPR (match_dup 1)
+ (match_dup 2)))]
+ "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
+ "@
+ sl<wd>. %0,%1,%2
+ #"
+ [(set_attr "length" "4,8")
+ (set_attr "dot" "yes,no")
+ (set_attr "type" "var_shift_rotate") ; var_delayed_compare
+])
+
+(define_split
+ [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+ (compare:CC
+ (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
+ (match_operand:SI 2 "gpc_reg_operand" ""))
+ (const_int 0)))
+ (set (match_operand:GPR 0 "gpc_reg_operand" "")
+ (ashift:GPR (match_dup 1)
+ (match_dup 2)))]
+ "(<MODE>mode == Pmode && rs6000_gen_cell_microcode)
+ && (reload_completed)"
+ [(set (match_dup 0)
+ (ashift:GPR (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 3)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ "")
+
+(define_insn "*ashl<mode>3_imm"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+ (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "const_int_operand" "i")))]
+ "UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
+ "sl<wd>i %0,%1,%2"
+ [(set_attr "type" "shift") ; delayed_compare
+])
+
+(define_insn "*ashl<mode>3_imm_dot"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+ (compare:CC
+ (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
+ (match_operand:SI 2 "const_int_operand" "i,i"))
+ (const_int 0)))
+ (clobber (match_scratch:GPR 0 "=r,r"))]
+ "(UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode))
+ && (<MODE>mode == Pmode && rs6000_gen_cell_microcode)"
+ "@
+ sl<wd>i. %0,%1,%2
+ #"
+ [(set_attr "length" "4,8")
+ (set_attr "dot" "yes,no")
+ (set_attr "type" "shift") ; delayed_compare
+])
+
+(define_split
+ [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+ (compare:CC
+ (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
+ (match_operand:SI 2 "const_int_operand" ""))
+ (const_int 0)))
+ (clobber (match_scratch:GPR 0 ""))]
+ "((UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode))
+ && (<MODE>mode == Pmode && rs6000_gen_cell_microcode))
+ && (reload_completed)"
+ [(set (match_dup 0)
+ (ashift:GPR (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 3)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ "")
+
+(define_insn "*ashl<mode>3_imm_dot2"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+ (compare:CC
+ (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
+ (match_operand:SI 2 "const_int_operand" "i,i"))
+ (const_int 0)))
+ (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
+ (ashift:GPR (match_dup 1)
+ (match_dup 2)))]
+ "(UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode))
+ && (<MODE>mode == Pmode && rs6000_gen_cell_microcode)"
+ "@
+ sl<wd>i. %0,%1,%2
+ #"
+ [(set_attr "length" "4,8")
+ (set_attr "dot" "yes,no")
+ (set_attr "type" "shift") ; delayed_compare
+])
+
+(define_split
+ [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+ (compare:CC
+ (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
+ (match_operand:SI 2 "const_int_operand" ""))
+ (const_int 0)))
+ (set (match_operand:GPR 0 "gpc_reg_operand" "")
+ (ashift:GPR (match_dup 1)
+ (match_dup 2)))]
+ "((UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode))
+ && (<MODE>mode == Pmode && rs6000_gen_cell_microcode))
+ && (reload_completed)"
+ [(set (match_dup 0)
+ (ashift:GPR (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 3)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ "")
+
(define_insn "lshr<mode>3"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
diff --git a/gcc/config/rs6000/integer.mdm b/gcc/config/rs6000/integer.mdm
index 7dd68dc..bb426b3 100644
--- a/gcc/config/rs6000/integer.mdm
+++ b/gcc/config/rs6000/integer.mdm
@@ -28,6 +28,26 @@
; slw[.], srw[.], srawi[.], sraw[.], sld[.], srd[.], sradi[.], srad[.]
+(define_dot_insn "ashl<mode>3"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+ (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "gpc_reg_operand" "r")))]
+ ""
+ "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
+ "sl<wd> %0,%1,%2"
+ [(set_attr "type" "var_shift_rotate") ; var_delayed_compare
+])
+
+(define_dot_insn "*ashl<mode>3_imm"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+ (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "const_int_operand" "i")))]
+ "UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
+ "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
+ "sl<wd>i %0,%1,%2"
+ [(set_attr "type" "shift") ; delayed_compare
+])
+
(define_dot_insn "lshr<mode>3"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index f28003d..8765340 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -4136,16 +4136,6 @@ (define_split
(const_int 0)))]
"")
-(define_insn "ashlsi3"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
- ""
- "@
- slw %0,%1,%2
- slwi %0,%1,%h2"
- [(set_attr "type" "var_shift_rotate,shift")])
-
(define_insn "*ashlsi3_64"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(zero_extend:DI
@@ -4157,66 +4147,6 @@ (define_insn "*ashlsi3_64"
slwi %0,%1,%h2"
[(set_attr "type" "var_shift_rotate,shift")])
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand"
"r,i,r,i"))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r,r,r"))]
- "TARGET_32BIT"
- "@
- slw. %3,%1,%2
- slwi. %3,%1,%h2
- #
- #"
- [(set_attr "type"
"var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
- (set_attr "length" "4,4,8,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))]
- "TARGET_32BIT && reload_completed"
- [(set (match_dup 3)
- (ashift:SI (match_dup 1) (match_dup 2)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand"
"r,i,r,i"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
- (ashift:SI (match_dup 1) (match_dup 2)))]
- "TARGET_32BIT"
- "@
- slw. %0,%1,%2
- slwi. %0,%1,%h2
- #
- #"
- [(set_attr "type"
"var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
- (set_attr "length" "4,4,8,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (ashift:SI (match_dup 1) (match_dup 2)))]
- "TARGET_32BIT && reload_completed"
- [(set (match_dup 0)
- (ashift:SI (match_dup 1) (match_dup 2)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
(define_insn "rlwinm"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
@@ -7372,83 +7302,6 @@ (define_split
(const_int 0)))]
"")
-(define_expand "ashldi3"
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" "")))]
- "TARGET_POWERPC64"
- "")
-
-(define_insn "*ashldi3_internal1"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
- "TARGET_POWERPC64"
- "@
- sld %0,%1,%2
- sldi %0,%1,%H2"
- [(set_attr "type" "var_shift_rotate,shift")])
-
-(define_insn "*ashldi3_internal2"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand"
"r,i,r,i"))
- (const_int 0)))
- (clobber (match_scratch:DI 3 "=r,r,r,r"))]
- "TARGET_64BIT"
- "@
- sld. %3,%1,%2
- sldi. %3,%1,%H2
- #
- #"
- [(set_attr "type"
"var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
- (set_attr "length" "4,4,8,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:DI 3 ""))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 3)
- (ashift:DI (match_dup 1) (match_dup 2)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn "*ashldi3_internal3"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand"
"r,i,r,i"))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
- (ashift:DI (match_dup 1) (match_dup 2)))]
- "TARGET_64BIT"
- "@
- sld. %0,%1,%2
- sldi. %0,%1,%H2
- #
- #"
- [(set_attr "type"
"var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
- (set_attr "length" "4,4,8,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (ashift:DI (match_dup 1) (match_dup 2)))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 0)
- (ashift:DI (match_dup 1) (match_dup 2)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
(define_insn "*ashldi3_internal4"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
--
1.8.1.4
