On May 10th, the Power Architecture Advisory Council announced the public availability of Power ISA 2.07. https://www.power.org/documentation/power-isa-version-2-07/
I will start submitting patches shortly which are our initial support for the future power8 cpu which will implement the ISA 2.07 instructions. Changes that will involve GCC support will include: 1) Add new builtins for cryptography support; 2) Add new builtins for vector operations (population count, count leading zeros, new vector logical instructions); 3) Support for vector long long (i.e. V2DI) add, subtract, compare operations; 4) Support for new instructions to move data between the general purpose registers and the VSX registers (direct move); 5) Support for quad memory atomic operations, and the ability to use the quad memory instructions (lq/stq) in user space; 6) VSX versions of the scalar single precision floating instructions; 7) Hardware transactional memory support; 8) 32-bit vector integer (i.e. V4SI) multiply operations; 9) Better support for unaligned vector memory operations; 10) Support for fusion, where the hardware can fusion certain add immediate instrucitons with the dependent load instruction; 11) Power8 scheduling support. Note, in order to build code for power8, you will need a power8 assembler, which will shortly be submitted to the binutils mailing lists. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460, USA email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
