[PATCH, AArch64] Support BFI instruction and insv standard pattern

[Ian Bolton]

Hi,

This patch implements the BFI variant of BFM.  In doing so, it also
implements the insv standard pattern.

I've regression tested on bare-metal and linux.

It comes complete with its own compilation and execution testcase.

OK for trunk?

Cheers,
Ian


2013-05-08  Ian Bolton  <ian.bol...@arm.com>

gcc/
        * config/aarch64/aarch64.md (insv): New define_expand.
        (*insv_reg<mode>): New define_insn.

testsuite/
        * gcc.target/aarch64/bfm_1.c: New test.
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 330f78c..b730ed0 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -3118,6 +3118,53 @@
    (set_attr "mode" "<MODE>")]
 )
 
+;; Bitfield Insert (insv)
+(define_expand "insv<mode>"
+  [(set (zero_extract:GPI (match_operand:GPI 0 "register_operand")
+                         (match_operand 1 "const_int_operand")
+                         (match_operand 2 "const_int_operand"))
+       (match_operand:GPI 3 "general_operand"))]
+  ""
+{
+  HOST_WIDE_INT mask = ((HOST_WIDE_INT)1 << INTVAL (operands[1])) - 1;
+
+  if (GET_MODE_BITSIZE (<MODE>mode) > BITS_PER_WORD
+      || INTVAL (operands[1]) < 1
+      || INTVAL (operands[1]) >= GET_MODE_BITSIZE (<MODE>mode)
+      || INTVAL (operands[2]) < 0
+      || (INTVAL (operands[2]) + INTVAL (operands[1]))
+         > GET_MODE_BITSIZE (<MODE>mode))
+    FAIL;
+
+  /* Prefer AND/OR for inserting all zeros or all ones.         */
+  if (CONST_INT_P (operands[3])
+      && ((INTVAL (operands[3]) & mask) == 0
+         || (INTVAL (operands[3]) & mask) == mask))
+    FAIL;
+
+  if (!register_operand (operands[3], <MODE>mode))
+    operands[3] = force_reg (<MODE>mode, operands[3]);
+
+  /* Intentional fall-through, which will lead to below pattern
+     being matched.  */
+})
+
+(define_insn "*insv_reg<mode>"
+  [(set (zero_extract:GPI (match_operand:GPI 0 "register_operand" "+r")
+                         (match_operand 1 "const_int_operand" "n")
+                         (match_operand 2 "const_int_operand" "n"))
+       (match_operand:GPI 3 "register_operand" "r"))]
+  "!(GET_MODE_BITSIZE (<MODE>mode) > BITS_PER_WORD
+      || INTVAL (operands[1]) < 1
+      || INTVAL (operands[1]) >= GET_MODE_BITSIZE (<MODE>mode)
+      || INTVAL (operands[2]) < 0
+      || (INTVAL (operands[2]) + INTVAL (operands[1]))
+         > GET_MODE_BITSIZE (<MODE>mode))"
+  "bfi\\t%<w>0, %<w>3, %2, %1"
+  [(set_attr "v8type" "bfm")
+   (set_attr "mode" "<MODE>")]
+)
+
 (define_insn "*<optab><ALLX:mode>_shft_<GPI:mode>"
   [(set (match_operand:GPI 0 "register_operand" "=r")
        (ashift:GPI (ANY_EXTEND:GPI
diff --git a/gcc/testsuite/gcc.target/aarch64/bfm_1.c 
b/gcc/testsuite/gcc.target/aarch64/bfm_1.c
new file mode 100644
index 0000000..d9a73a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/bfm_1.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+typedef struct bitfield
+{
+  unsigned short eight: 8;
+  unsigned short four: 4;
+  unsigned short five: 5;
+  unsigned short seven: 7;
+} bitfield;
+
+bitfield
+bfi1 (bitfield a)
+{
+  /* { dg-final { scan-assembler "bfi\tw\[0-9\]+, w\[0-9\]+, 0, 8" } } */
+  a.eight = 3;
+  return a;
+}
+
+bitfield
+bfi2 (bitfield a)
+{
+  /* { dg-final { scan-assembler "bfi\tw\[0-9\]+, w\[0-9\]+, 16, 5" } } */
+  a.five = 7;
+  return a;
+}
+
+int
+main (int argc, char** argv)
+{
+  bitfield a;
+  bitfield b = bfi1 (a);
+  bitfield c = bfi2 (b);
+
+  if (c.eight != 3)
+    abort ();
+
+  if (c.five != 7)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */