On 30/01/13 15:54, Kyrylo Tkachov wrote:
Hi all,This patch implements the atomic built-ins using the new ARMv8 load-acquire and store-release instructions. They allow us to generate barrier-free code for a variety of atomic operations such as: atomic load, atomic store, atomic compare and swap, atomic {or, and, add, sub, xor}. Tests will come in a separate patch soon. No regressions on arm-none-eabi. Bootstrap on armv7l-unknown-linux-gnueabihf successful. Ok for trunk (now or when stage 1 reopens)? Thanks, Kyrill gcc/ChangeLog 2013-01-23 Kyrylo Tkachov <kyrylo.tkachov at arm.com> * config/arm/arm.c (arm_emit_load_exclusive): Add acq parameter. Emit load-acquire versions when acq is true. (arm_emit_store_exclusive): Add rel parameter. Emit store-release versions when rel is true. (arm_split_compare_and_swap): Use acquire-release instructions instead of barriers when appropriate. (arm_split_atomic_op): Likewise. * config/arm/arm.h (TARGET_HAVE_LDACQ): New macro. * config/arm/unspecs.md (VUNSPEC_LAX): New unspec. (VUNSPEC_SLX): Likewise. (VUNSPEC_LDA): Likewise. (VUNSPEC_STL): Likewise. * config/arm/sync.md (atomic_load<mode>): New pattern. (atomic_store<mode>): Likewise. (arm_load_acquire_exclusive<mode>): Likewise. (arm_load_acquire_exclusivesi): Likewise. (arm_load_acquire_exclusivedi): Likewise. (arm_store_release_exclusive<mode>): Likewise. atomics.txt @@ -26067,6 +26099,15 @@ arm_expand_compare_and_swap (rtx operands[]) mod_f = operands[7]; mode = GET_MODE (mem); + /* Normally the succ memory model must be stronger than fail, but in the + unlikely event of fail being ACQUIRE and succ being RELEASE we need to + promote succ to ACQ_REL so that we don't lose the acquire semantics. */
Can you double check the indentation here. The 'u' from 'unlikely' should line up with the 'N' from 'Normally'.
Otherwise OK. R. Ca
