The mode for AND should really be CC_NZ, so I fixed that up and in the TST
patterns that (erroneously) expected it to be CC mode.
It has been tested on linux and bare-metal.
OK to commit to trunk (as bug fix)?
Thanks.
Ian
13-02-01 Ian Bolton <ian.bol...@arm.com>
* config/aarch64/aarch64.c (aarch64_select_cc_mode): Return correct
CC mode for AND.
* config/aarch64/aarch64.md (*and<mode>3nr_compare0): Fixed to use
CC_NZ.
(*and_<SHIFT:optab><mode>3nr_compare0): Likewise.
---------------------------------
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 03b1361..2b09669 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -3076,7 +3076,7 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
if ((GET_MODE (x) == SImode || GET_MODE (x) == DImode)
&& y == const0_rtx
&& (code == EQ || code == NE || code == LT || code == GE)
- && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS))
+ && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS || GET_CODE (x) ==
AND))
return CC_NZmode;
/* A compare with a shifted operand. Because of canonicalization,
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 36267c9..c4c152f 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -2470,8 +2470,8 @@
)
(define_insn "*and<mode>3nr_compare0"
- [(set (reg:CC CC_REGNUM)
- (compare:CC
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(and:GPI (match_operand:GPI 0 "register_operand" "%r,r")
(match_operand:GPI 1 "aarch64_logical_operand"
"r,<lconst>"))
(const_int 0)))]
@@ -2481,8 +2481,8 @@
(set_attr "mode" "<MODE>")])
(define_insn "*and_<SHIFT:optab><mode>3nr_compare0"
- [(set (reg:CC CC_REGNUM)
- (compare:CC
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(and:GPI (SHIFT:GPI
(match_operand:GPI 0 "register_operand" "r")
(match_operand:QI 1 "aarch64_shift_imm_<mode>" "n"))
