Hello!
While looking at recent Andi's atomic patches, I noticed that memory
model operand is not properly masked in a couple of i386 sync.md
patterns.
2013-01-13 Uros Bizjak <ubiz...@gmail.com>
* config/i386/sync.md (mem_thread_fence): Mask operands[0] with
MEMMODEL_MASK to determine memory model.
(atomic_store<mode>): Ditto from operands[2].
* config/i386/i386.c (ix86_memmodel_check): Declare "strong" as bool.
Tested on x86_64-pc-linux-gnu {,-m32}, committed to mainline SVN as obvious.
The patch will be also committed to 4.7 branch.
Uros.
Index: i386.c
===================================================================
--- i386.c (revision 195133)
+++ i386.c (working copy)
@@ -42082,7 +42082,7 @@ static unsigned HOST_WIDE_INT
ix86_memmodel_check (unsigned HOST_WIDE_INT val)
{
unsigned HOST_WIDE_INT model = val & MEMMODEL_MASK;
- unsigned HOST_WIDE_INT strong;
+ bool strong;
if (val & ~(unsigned HOST_WIDE_INT)(IX86_HLE_ACQUIRE|IX86_HLE_RELEASE
|MEMMODEL_MASK)
Index: sync.md
===================================================================
--- sync.md (revision 195133)
+++ sync.md (working copy)
@@ -101,9 +101,11 @@
[(match_operand:SI 0 "const_int_operand")] ;; model
""
{
+ enum memmodel model = (enum memmodel) (INTVAL (operands[0]) & MEMMODEL_MASK);
+
/* Unless this is a SEQ_CST fence, the i386 memory model is strong
enough not to require barriers of any kind. */
- if (INTVAL (operands[0]) == MEMMODEL_SEQ_CST)
+ if (model == MEMMODEL_SEQ_CST)
{
rtx (*mfence_insn)(rtx);
rtx mem;
@@ -200,7 +202,7 @@
UNSPEC_MOVA))]
""
{
- enum memmodel model = (enum memmodel) INTVAL (operands[2]);
+ enum memmodel model = (enum memmodel) (INTVAL (operands[2]) & MEMMODEL_MASK);
if (<MODE>mode == DImode && !TARGET_64BIT)
{
