From: "Luke Zhuang" <[email protected]>
An LRA crashing is found by fuzz-testing, and is triggered by
<0748d2c83fc>. We can avoid it by replacing RVVM8QI with RVVM1QI,
and may need to fix the LRA later.
A reduced test is appended as well, demonstrating the crash.
gcc/ChangeLog:
* config/riscv/riscv.md (@tlsdesc<mode>): Use individual
RVVM1QI clobbers instead of four RVVM8QI.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/tlsdesc_clobber_lra.c: New test.
Co-authored-by: Kito Cheng <[email protected]>
---
gcc/config/riscv/riscv.md | 36 ++++++++++++++++---
.../gcc.target/riscv/tlsdesc_clobber_lra.c | 16 +++++++++
2 files changed, 48 insertions(+), 4 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/tlsdesc_clobber_lra.c
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index c64e4ff3c77..e97f190e444 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2480,10 +2480,38 @@
[(match_operand:P 0 "symbolic_operand" "")]
UNSPEC_TLSDESC))
(clobber (reg:P T0_REGNUM))
- (clobber (reg:RVVM8QI 96))
- (clobber (reg:RVVM8QI 104))
- (clobber (reg:RVVM8QI 112))
- (clobber (reg:RVVM8QI 120))
+ (clobber (reg:RVVM1QI 96))
+ (clobber (reg:RVVM1QI 97))
+ (clobber (reg:RVVM1QI 98))
+ (clobber (reg:RVVM1QI 99))
+ (clobber (reg:RVVM1QI 100))
+ (clobber (reg:RVVM1QI 101))
+ (clobber (reg:RVVM1QI 102))
+ (clobber (reg:RVVM1QI 103))
+ (clobber (reg:RVVM1QI 104))
+ (clobber (reg:RVVM1QI 105))
+ (clobber (reg:RVVM1QI 106))
+ (clobber (reg:RVVM1QI 107))
+ (clobber (reg:RVVM1QI 108))
+ (clobber (reg:RVVM1QI 109))
+ (clobber (reg:RVVM1QI 110))
+ (clobber (reg:RVVM1QI 111))
+ (clobber (reg:RVVM1QI 112))
+ (clobber (reg:RVVM1QI 113))
+ (clobber (reg:RVVM1QI 114))
+ (clobber (reg:RVVM1QI 115))
+ (clobber (reg:RVVM1QI 116))
+ (clobber (reg:RVVM1QI 117))
+ (clobber (reg:RVVM1QI 118))
+ (clobber (reg:RVVM1QI 119))
+ (clobber (reg:RVVM1QI 120))
+ (clobber (reg:RVVM1QI 121))
+ (clobber (reg:RVVM1QI 122))
+ (clobber (reg:RVVM1QI 123))
+ (clobber (reg:RVVM1QI 124))
+ (clobber (reg:RVVM1QI 125))
+ (clobber (reg:RVVM1QI 126))
+ (clobber (reg:RVVM1QI 127))
(clobber (reg:SI VL_REGNUM))
(clobber (reg:SI VTYPE_REGNUM))
(clobber (reg:SI VXRM_REGNUM))
diff --git a/gcc/testsuite/gcc.target/riscv/tlsdesc_clobber_lra.c
b/gcc/testsuite/gcc.target/riscv/tlsdesc_clobber_lra.c
new file mode 100644
index 00000000000..307a42d8ec0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/tlsdesc_clobber_lra.c
@@ -0,0 +1,16 @@
+/* Verify we don't ICE on the following test case. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target tls_native } */
+/* { dg-options "-O -fpic -mtls-dialect=desc -march=rv64gcv -mabi=lp64d" } */
+/* { dg-require-effective-target fpic } */
+
+extern __thread int x;
+extern int bar(int);
+
+int f(int id) {
+ x = id * 1000;
+ bar(0);
+ if (x != id * 1000) return bar(x);
+ return 0;
+}
--
2.47.1
