Hi gcc-patches mailing list, Richard Ball via Sourceware Forge <[email protected]> has requested that the following forgejo pull request be published on the mailing list.
Created on: 2026-05-31 11:26:06+00:00 Latest update: 2026-07-15 12:36:35+00:00 Changes: 11 changed files, 311 additions, 3 deletions Head revision: ricbal02/gcc-TEST ref f16f32dot commit a33b47becad2668c91cebf026272d0107c612ce4 Base revision: gcc/gcc-TEST ref trunk commit 9e9e22587f7954e079ac68e0e878f1feec7977f8 r17-2414-g9e9e22587f7954 Merge base: 9e9e22587f7954e079ac68e0e878f1feec7977f8 Full diff url: https://forge.sourceware.org/gcc/gcc-TEST/pulls/166.diff Discussion: https://forge.sourceware.org/gcc/gcc-TEST/pulls/166 Requested Reviewers: karmea01 This patch adds the following advsimd intrinsics: *vdot_f32_f16 *vdotq_f32_f16 *vdot_lane_f32_f16 *vdot_laneq_f32_f16 *vdotq_lane_f32_f16 *vdotq_laneq_f32_f16 gcc/ChangeLog: * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): New target flag. * config/aarch64/aarch64-simd-builtins.def: New functions. * config/aarch64/aarch64-simd.md (aarch64_simdfdot<mode>): New pattern. (aarch64_simdfdot_lane<VF:isquadop><VDQSF:mode>): Likewise. * config/aarch64/aarch64.h (TARGET_F16F32DOT): New target flag. * config/aarch64/arm_neon.h (target): Add f16f32dot section (__attribute__): New builtin function calls. (vdot_f32_f16): Likewise. (vdotq_f32_f16): Likewise. (vdot_lane_f32_f16): Likewise. (vdot_laneq_f32_f16): Likewise. (vdotq_lane_f32_f16): Likewise. (vdotq_laneq_f32_f16): Likewise. * config/aarch64/iterators.md (q): New options for isquadop. * doc/invoke.texi: Add f16f32dot. gcc/testsuite/ChangeLog: * lib/target-supports.exp: New check_effective_target. * gcc.target/aarch64/advsimd-intrinsics/fdot-1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/fdot-2.c: New test. * gcc.target/aarch64/advsimd-intrinsics/fdot-3.c: New test. Changed files: - A: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/fdot-1.c - A: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/fdot-2.c - A: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/fdot-3.c - M: gcc/config/aarch64/aarch64-c.cc - M: gcc/config/aarch64/aarch64-simd-builtins.def - M: gcc/config/aarch64/aarch64-simd.md - M: gcc/config/aarch64/aarch64.h - M: gcc/config/aarch64/arm_neon.h - M: gcc/config/aarch64/iterators.md - M: gcc/doc/invoke.texi - M: gcc/testsuite/lib/target-supports.exp Richard Ball (1): aarch64: Add Support for F16F32DOT gcc/config/aarch64/aarch64-c.cc | 1 + gcc/config/aarch64/aarch64-simd-builtins.def | 6 ++ gcc/config/aarch64/aarch64-simd.md | 30 ++++++++ gcc/config/aarch64/aarch64.h | 2 + gcc/config/aarch64/arm_neon.h | 50 +++++++++++++ gcc/config/aarch64/iterators.md | 12 +++- gcc/doc/invoke.texi | 2 + .../aarch64/advsimd-intrinsics/fdot-1.c | 68 ++++++++++++++++++ .../aarch64/advsimd-intrinsics/fdot-2.c | 70 +++++++++++++++++++ .../aarch64/advsimd-intrinsics/fdot-3.c | 32 +++++++++ gcc/testsuite/lib/target-supports.exp | 41 +++++++++++ 11 files changed, 311 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/fdot-1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/fdot-2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/fdot-3.c Range-diff against v1: 1: 865aa2447fca ! 1: a33b47becad2 aarch64: Add Support for F16F32DOT @@ Commit message gcc/ChangeLog: - * config/aarch64/aarch64-c.cc - (aarch64_update_cpp_builtins): New target flag. - * config/aarch64/aarch64-simd-builtins.def: New functions. - * config/aarch64/aarch64-simd.md - (aarch64_simdfdot<mode>): New pattern. - (aarch64_simdfdot_lane<VF:isquadop><VDQSF:mode>): Likewise. - * config/aarch64/aarch64.h - (TARGET_F16F32DOT): New target flag. - * config/aarch64/arm_neon.h - (target): Add f16f32dot section - (__attribute__): New builtin function calls. - (vdot_f32_f16): Likewise. - (vdotq_f32_f16): Likewise. - (vdot_lane_f32_f16): Likewise. - (vdot_laneq_f32_f16): Likewise. - (vdotq_lane_f32_f16): Likewise. - (vdotq_laneq_f32_f16): Likewise. - * config/aarch64/iterators.md (q): New options for isquadop. - * doc/invoke.texi: Add f16f32dot. + * config/aarch64/aarch64-c.cc + (aarch64_update_cpp_builtins): New target flag. + * config/aarch64/aarch64-simd-builtins.def: New functions. + * config/aarch64/aarch64-simd.md + (aarch64_simdfdot<mode>): New pattern. + (aarch64_simdfdot_lane<VF:isquadop><VDQSF:mode>): Likewise. + * config/aarch64/aarch64.h + (TARGET_F16F32DOT): New target flag. + * config/aarch64/arm_neon.h + (target): Add f16f32dot section + (__attribute__): New builtin function calls. + (vdot_f32_f16): Likewise. + (vdotq_f32_f16): Likewise. + (vdot_lane_f32_f16): Likewise. + (vdot_laneq_f32_f16): Likewise. + (vdotq_lane_f32_f16): Likewise. + (vdotq_laneq_f32_f16): Likewise. + * config/aarch64/iterators.md (q): New options for isquadop. + * doc/invoke.texi: Add f16f32dot. gcc/testsuite/ChangeLog: - * lib/target-supports.exp: New check_effective_target. - * gcc.target/aarch64/advsimd-intrinsics/fdot-1.c: New test. - * gcc.target/aarch64/advsimd-intrinsics/fdot-2.c: New test. - * gcc.target/aarch64/advsimd-intrinsics/fdot-3.c: New test. + * lib/target-supports.exp: New check_effective_target. + * gcc.target/aarch64/advsimd-intrinsics/fdot-1.c: New test. + * gcc.target/aarch64/advsimd-intrinsics/fdot-2.c: New test. + * gcc.target/aarch64/advsimd-intrinsics/fdot-3.c: New test. ## gcc/config/aarch64/aarch64-c.cc ## @@ gcc/config/aarch64/aarch64-c.cc: aarch64_update_cpp_builtins (cpp_reader *pfile) - aarch64_def_or_undef (TARGET_SME2p2, "__ARM_FEATURE_SME2p2", pfile); - aarch64_def_or_undef (TARGET_FAMINMAX, "__ARM_FEATURE_FAMINMAX", pfile); - aarch64_def_or_undef (TARGET_PCDPHINT, "__ARM_FEATURE_PCDPHINT", pfile); + aarch64_def_or_undef (AARCH64_HAVE_ISA (SSVE_FEXPA), + "__ARM_FEATURE_SSVE_FEXPA", pfile); + builtin_define ("__ARM_PREFETCH_RANGE"); + aarch64_def_or_undef (TARGET_F16F32DOT, "__ARM_FEATURE_F16F32DOT", pfile); // Function multi-versioning defines @@ gcc/config/aarch64/aarch64-simd-builtins.def VAR2 (QUADOP_LANE_PAIR, bfdot_lane, 0, QUIET, v2sf, v4sf) VAR2 (QUADOP_LANE_PAIR, bfdot_laneq, 0, QUIET, v2sf, v4sf) -+ /* Implemented by aarch64_simdfdot{_lane}{q}<mode>. */ -+ VAR2 (TERNOP, simdfdot, 0, QUIET, v2sf, v4sf) -+ VAR2 (QUADOP_LANE_PAIR, simdfdot_lane, 0, QUIET, v2sf, v4sf) -+ VAR2 (QUADOP_LANE_PAIR, simdfdot_laneq, 0, QUIET, v2sf, v4sf) ++ /* Implemented by sdot_prod<mode>. */ ++ BUILTIN_VF (TERNOP, sdot_prod, 10, DEFAULT) ++ /* Implemented by sdot_lane{q}<dot_mode>. */ ++ BUILTIN_VF (QUADOP_LANE_PAIR, sdot_lane, 10, DEFAULT) ++ BUILTIN_VF (QUADOP_LANE_PAIR, sdot_laneq, 10, DEFAULT) + /* Implemented by aarch64_bfmmlaqv4sf */ VAR1 (TERNOP, bfmmlaq, 0, QUIET, v4sf) @@ gcc/config/aarch64/aarch64-simd-builtins.def ## gcc/config/aarch64/aarch64-simd.md ## @@ - [(set_attr "type" "neon_dot<VDQSF:q>")] + [(set_attr "type" "neon_dot<VS:q>")] ) -+(define_insn "aarch64_simdfdot<mode>" ++(define_insn "sdot_prod<VDQSF:vsi2qi><vczle><vczbe>" + [(set (match_operand:VDQSF 0 "register_operand" "=w") + (plus:VDQSF + (unspec:VDQSF -+ [(match_operand:<VFMLA_W> 2 "register_operand" "w") -+ (match_operand:<VFMLA_W> 3 "register_operand" "w")] ++ [(match_operand:<VSI2QI> 2 "register_operand" "w") ++ (match_operand:<VSI2QI> 3 "register_operand" "w")] + UNSPEC_FDOT) + (match_operand:VDQSF 1 "register_operand" "0")))] + "TARGET_F16F32DOT" @@ gcc/config/aarch64/aarch64-simd.md + [(set_attr "type" "neon_dot<q>")] +) + -+(define_insn "aarch64_simdfdot_lane<VF:isquadop><VDQSF:mode>" ++(define_insn "sdot_lane<VF:isquadop><VDQSF:vsi2qi><vczle><vczbe>" + [(set (match_operand:VDQSF 0 "register_operand" "=w") + (plus:VDQSF + (unspec:VDQSF -+ [(match_operand:<VDQSF:VFMLA_W> 2 "register_operand" "w") ++ [(match_operand:<VDQSF:VSI2QI> 2 "register_operand" "w") + (match_operand:VF 3 "register_operand" "w") -+ (match_operand:SI 4 "const_int_operand" "n")] ++ (match_operand:SI 4 "immediate_operand" "i")] + UNSPEC_FDOT) + (match_operand:VDQSF 1 "register_operand" "0")))] + "TARGET_F16F32DOT" +{ -+ int nunits = GET_MODE_NUNITS (<VF:MODE>mode).to_constant (); -+ int lane = INTVAL (operands[4]); -+ operands[4] = gen_int_mode (ENDIAN_LANE_N (nunits / 2, lane), SImode); ++ operands[4] = aarch64_endian_lane_rtx (<VF:MODE>mode, INTVAL (operands[4])); + return "fdot\t%0.<VDQSF:Vtype>, %2.<VDQSF:Vbfdottype>, %3.2h[%4]"; +} + [(set_attr "type" "neon_dot<VDQSF:q>")] +) + - ;; bfmmla - (define_insn "aarch64_bfmmlaqv4sf" - [(set (match_operand:V4SF 0 "register_operand" "=w") + (define_expand "copysign<mode>3" + [(match_operand:VHSDF 0 "register_operand") + (match_operand:VHSDF 1 "register_operand") ## gcc/config/aarch64/aarch64.h ## @@ gcc/config/aarch64/aarch64.h: constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED @@ gcc/config/aarch64/arm_neon.h: vst4q_lane_bf16 (bfloat16_t *__ptr, bfloat16x8x4_ +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vdot_f32_f16 (float32x2_t __r, float16x4_t __a, float16x4_t __b) +{ -+ return __builtin_aarch64_simdfdotv2sf (__r, __a, __b); ++ return __builtin_aarch64_sdot_prodv4hf (__r, __a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vdotq_f32_f16 (float32x4_t __r, float16x8_t __a, float16x8_t __b) +{ -+ return __builtin_aarch64_simdfdotv4sf (__r, __a, __b); ++ return __builtin_aarch64_sdot_prodv8hf (__r, __a, __b); +} + +__extension__ extern __inline float32x2_t @@ gcc/config/aarch64/arm_neon.h: vst4q_lane_bf16 (bfloat16_t *__ptr, bfloat16x8x4_ +vdot_lane_f32_f16 (float32x2_t __r, float16x4_t __a, float16x4_t __b, + const int __index) +{ -+ return __builtin_aarch64_simdfdot_lanev2sf (__r, __a, __b, __index); ++ return __builtin_aarch64_sdot_lanev4hf (__r, __a, __b, __index); +} + +__extension__ extern __inline float32x2_t @@ gcc/config/aarch64/arm_neon.h: vst4q_lane_bf16 (bfloat16_t *__ptr, bfloat16x8x4_ +vdot_laneq_f32_f16 (float32x2_t __r, float16x4_t __a, float16x8_t __b, + const int __index) +{ -+ return __builtin_aarch64_simdfdot_laneqv2sf (__r, __a, __b, __index); ++ return __builtin_aarch64_sdot_laneqv4hf (__r, __a, __b, __index); +} + +__extension__ extern __inline float32x4_t @@ gcc/config/aarch64/arm_neon.h: vst4q_lane_bf16 (bfloat16_t *__ptr, bfloat16x8x4_ +vdotq_lane_f32_f16 (float32x4_t __r, float16x8_t __a, float16x4_t __b, + const int __index) +{ -+ return __builtin_aarch64_simdfdot_lanev4sf (__r, __a, __b, __index); ++ return __builtin_aarch64_sdot_lanev8hf (__r, __a, __b, __index); +} + +__extension__ extern __inline float32x4_t @@ gcc/config/aarch64/arm_neon.h: vst4q_lane_bf16 (bfloat16_t *__ptr, bfloat16x8x4_ +vdotq_laneq_f32_f16 (float32x4_t __r, float16x8_t __a, float16x8_t __b, + const int __index) +{ -+ return __builtin_aarch64_simdfdot_laneqv4sf (__r, __a, __b, __index); ++ return __builtin_aarch64_sdot_laneqv8hf (__r, __a, __b, __index); +} + +#pragma GCC pop_options @@ gcc/config/aarch64/iterators.md ;; addresses in different modes. In LP64, only DI will match, while in ;; ILP32, either can match. @@ + (V4HF "v") (V8HF "v")]) + + (define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi") +- (VNx4SI "vnx16qi") (VNx2DI "vnx8hi")]) ++ (VNx4SI "vnx16qi") (VNx2DI "vnx8hi") ++ (V2SF "v4hf") (V4SF "v8hf")]) + (define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI") +- (VNx4SI "VNx16QI") (VNx2DI "VNx8HI")]) ++ (VNx4SI "VNx16QI") (VNx2DI "VNx8HI") ++ (V2SF "V4HF") (V4SF "V8HF")]) + + + ;; Register suffix for DOTPROD input types from the return type. +@@ (define_mode_attr f16quad [(V2SF "") (V4SF "q")]) @@ gcc/doc/invoke.texi: extension. ## gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/fdot-1.c (new) ## @@ +/* { dg-do assemble { target { aarch64*-*-* } } } */ -+/* { dg-require-effective-target aarch64_v8_2a_f16f32dot_neon_ok } */ -+/* { dg-add-options aarch64_v8_2a_f16f32dot_neon } */ ++/* { dg-require-effective-target aarch64_f16f32dot_neon_ok } */ ++/* { dg-add-options aarch64_f16f32dot_neon } */ +/* { dg-additional-options "-save-temps" } */ +/* { dg-final { check-function-bodies "**" "" {-O[^0]} } } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ @@ gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/fdot-2.c (new) @@ +/* { dg-do assemble { target { aarch64*-*-* } } } */ +/* { dg-require-effective-target stdint_types_mbig_endian } */ -+/* { dg-require-effective-target aarch64_v8_2a_f16f32dot_neon_ok } */ -+/* { dg-add-options aarch64_v8_2a_f16f32dot_neon } */ ++/* { dg-require-effective-target aarch64_f16f32dot_neon_ok } */ ++/* { dg-add-options aarch64_f16f32dot_neon } */ +/* { dg-additional-options "-mbig-endian --save-temps" } */ +/* { dg-final { check-function-bodies "**" "" {-O[^0]} } } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ @@ gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/fdot-3.c (new) @@ +/* { dg-do assemble { target { aarch64*-*-* } } } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ -+/* { dg-require-effective-target aarch64_v8_2a_f16f32dot_neon_ok } */ -+/* { dg-add-options aarch64_v8_2a_f16f32dot_neon } */ ++/* { dg-require-effective-target aarch64_f16f32dot_neon_ok } */ ++/* { dg-add-options aarch64_f16f32dot_neon } */ +/* { dg-additional-options "--save-temps" } */ + +#include <arm_neon.h> @@ gcc/testsuite/lib/target-supports.exp: proc add_options_for_arm_fp16fml_neon { f +# for AARCH64. +# Record the command line options needed. + -+proc check_effective_target_aarch64_v8_2a_f16f32dot_neon_ok_nocache { } { -+ global et_aarch64_v8_2a_f16f32dot_neon_flags -+ set et_aarch64_v8_2a_f16f32dot_neon_flags "" ++proc check_effective_target_aarch64_f16f32dot_neon_ok_nocache { } { ++ global et_aarch64_f16f32dot_neon_flags ++ set et_aarch64_f16f32dot_neon_flags "" + + if { ![istarget aarch64*-*-*] } { + return 0; + } + -+ foreach flags {"" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" "-mfloat-abi=hard -mfpu=neon-fp-armv8" } { -+ if { [check_no_compiler_messages_nocache aarch64_v8_2a_f16f32dot_neon_ok object { ++ foreach flags {"" "" } { ++ if { [check_no_compiler_messages_nocache aarch64_f16f32dot_neon_ok object { + #include <arm_neon.h> + #if !defined (__ARM_FEATURE_F16F32DOT) + #error "__ARM_FEATURE_F16F32DOT not defined" + #endif -+ } "$flags -march=armv8.2-a+f16f32dot"] } { -+ set et_aarch64_v8_2a_f16f32dot_neon_flags "$flags -march=armv8.2-a+f16f32dot" ++ } "$flags -march=armv8.2-a+fp16+f16f32dot"] } { ++ set et_aarch64_f16f32dot_neon_flags "$flags -march=armv8.2-a+fp16+f16f32dot" + return 1 + } + } @@ gcc/testsuite/lib/target-supports.exp: proc add_options_for_arm_fp16fml_neon { f + return 0; +} + -+proc check_effective_target_aarch64_v8_2a_f16f32dot_neon_ok { } { -+ return [check_cached_effective_target aarch64_v8_2a_f16f32dot_neon_ok \ -+ check_effective_target_aarch64_v8_2a_f16f32dot_neon_ok_nocache] ++proc check_effective_target_aarch64_f16f32dot_neon_ok { } { ++ return [check_cached_effective_target aarch64_f16f32dot_neon_ok \ ++ check_effective_target_aarch64_f16f32dot_neon_ok_nocache] +} + -+proc add_options_for_aarch64_v8_2a_f16f32dot_neon { flags } { -+ if { ! [check_effective_target_aarch64_v8_2a_f16f32dot_neon_ok] } { ++proc add_options_for_aarch64_f16f32dot_neon { flags } { ++ if { ! [check_effective_target_aarch64_f16f32dot_neon_ok] } { + return "$flags" + } -+ global et_aarch64_v8_2a_f16f32dot_neon_flags -+ return "$flags $et_aarch64_v8_2a_f16f32dot_neon_flags" ++ global et_aarch64_f16f32dot_neon_flags ++ return "$flags $et_aarch64_f16f32dot_neon_flags" +} + # Return 1 if the target supports BFloat16 SIMD instructions, 0 otherwise. -- 2.54.0
