AMD General Hi,
> -----Original Message----- > From: Jiang, Haochen <[email protected]> > Sent: Monday, July 6, 2026 9:02 AM > To: Kumar, Venkataramanan <[email protected]>; gcc- > [email protected] > Cc: Liu, Hongtao <[email protected]>; [email protected]; Sharma, > Dipesh <[email protected]> > Subject: RE: [PATCH 3/7] Support BSR0 register > > Caution: This message originated from an External Source. Use proper caution > when opening attachments, clicking links, or responding. > > > > From: Kumar, Venkataramanan <[email protected]> > > Sent: Monday, July 6, 2026 2:12 AM > > > > > From: Haochen Jiang <[email protected]> > > > Sent: Thursday, July 2, 2026 12:19 PM diff --git > > > a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index > > > 9cdd0138104..b00cf14d29a 100644 @@ -14077,6 +14091,7 @@ print_reg > > > (rtx x, int code, FILE *file) > > > putc (msize > 4 && TARGET_64BIT ? 'r' : 'e', file); > > > /* FALLTHRU */ > > > case 2: > > > + case 128: > > > > Can u comment here why 128 is added ?? We can also check like this > > REGNO == BSR0_REG ?? > > > > For BSR, the size is 128. So when you drop into this switch, it will hit > gcc_unreachable() unless you work around this by an if condition to keep the > same code path. I believe a case 128 should win versus a if condition work > around. Ok, the patch looks good. Regards, Venkat. > > Thx, > Haochen
