Add the `__ARM_FEATURE_SME_MOP4` feature test macro, and a test checking
that it is correctly defined. The `+sme-mop4` flag itself was added
earlier, but the feature test macro and documentation weren't added.
gcc/ChangeLog:
* doc/invoke.texi: Document new extension flags.
* config/aarch64/aarch64.h (TARGET_SME_MOP4): New target macro.
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Define
`__ARM_FEATURE_SME_MOP4` macros when the relevant extension is enabled.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/pragma_cpp_predefs_4.c: Test that
`__ARM_FEATURE_SME_F8F16`, `__ARM_FEATURE_SME_F8F32`
and `__ARM_FEATURE_SME_MOP4` macros are defined when the
relevant extension is enabled.
* lib/target-supports.exp: Add `sme-mop4` to `exts`.
---
gcc/config/aarch64/aarch64-c.cc | 2 ++
gcc/config/aarch64/aarch64.h | 2 ++
gcc/doc/invoke.texi | 3 +++
gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c | 7 +++++++
gcc/testsuite/lib/target-supports.exp | 2 +-
5 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc
index c4ddcc6d717..e01dc3b4e3e 100644
--- a/gcc/config/aarch64/aarch64-c.cc
+++ b/gcc/config/aarch64/aarch64-c.cc
@@ -312,6 +312,8 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
"__ARM_FEATURE_SME_F16F16", pfile);
aarch64_def_or_undef (TARGET_SME_F64F64, "__ARM_FEATURE_SME_F64F64", pfile);
aarch64_def_or_undef (TARGET_SME2, "__ARM_FEATURE_SME2", pfile);
+ aarch64_def_or_undef (AARCH64_HAVE_ISA (SME_MOP4), "__ARM_FEATURE_SME_MOP4",
+ pfile);
aarch64_def_or_undef (AARCH64_HAVE_ISA (SME2p1),
"__ARM_FEATURE_SME2p1", pfile);
aarch64_def_or_undef (TARGET_SME2p2, "__ARM_FEATURE_SME2p2", pfile);
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 26db4958a80..a62d1fbaf05 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -499,6 +499,8 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED
elements are enabled through +sme-lutv2. */
#define TARGET_SME_LUTv2 AARCH64_HAVE_ISA (SME_LUTv2)
+#define TARGET_SME_MOP4 (AARCH64_HAVE_ISA (SME_MOP4) && TARGET_STREAMING)
+
/* Prefer different predicate registers for the output of a predicated
operation over re-using an existing input predicate. */
#define TARGET_SVE_PRED_CLOBBER (TARGET_SVE \
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 354ceb76f53..e990e0f2bbd 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -22032,6 +22032,9 @@ and SVE_B16B16 instructions.
@item sme-f16f16
Enable the FEAT_SME_F16F16 extension to SME. This also enables SME2
instructions.
+@item sme-mop4
+Enable the FEAT_SME_MOP4 extension to SME. This also enables SME2
+instructions.
@item sme2p1
Enable the Scalable Matrix Extension version 2.1. This also enables SME2
instructions.
diff --git a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c
b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c
index fd85b40cc8d..7a2680bbc1f 100644
--- a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c
+++ b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c
@@ -231,6 +231,13 @@
#ifndef __ARM_FEATURE_SME2p2
#error Foo
#endif
+#pragma GCC target "+nothing+sve2+sme-mop4"
+#ifndef __ARM_FEATURE_SME_MOP4
+#error "__ARM_FEATURE_SME_MOP4 not defined"
+#endif
+#ifndef __ARM_FEATURE_SME2
+#error "__ARM_FEATURE_SME2 not defined"
+#endif
#pragma GCC target "branch-protection=standard"
#ifndef __ARM_FEATURE_BTI_DEFAULT
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index cab72c8a9e1..76fe64e6050 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -12914,7 +12914,7 @@ set exts {
"sme-f8f16" "sme-f8f32"
"sme-b16b16" "sme-f16f16" "sme-i16i64" "sme" "sme2" "sme2p1" "sme2p2"
"ssve-fp8dot2" "ssve-fp8dot4" "ssve-fp8fma" "sve-bfscale" "sme-lutv2"
- "ssve-fexpa" "ssve-bitperm" "ssve-aes"
+ "ssve-fexpa" "ssve-bitperm" "ssve-aes" "sme-mop4"
}
foreach { aarch64_ext } $exts {
--
2.51.0
