On 09/07/2026 18:26, Jeffrey Law wrote:
On 7/9/2026 10:08 AM, Andrew Stubbs wrote:
The ISA has only one way to load vectors*: a vector of absolute
addresses goes in, and a vector of data comes out. The address vector
needs to be in the VGPR_REGS register class.
Sounds fairly painful :-)
But, the compiler doesn't generate address vectors when it does stack
spills and reloads, so we also support the more normal base address
style of addressing, and then convert it later using a split. In that
case the base address needs to be in class SGPR_REGS (or else the
vec_duplicate instruction won't work).
You probably already explored the secondary register class path to get
the right register class. That's traditionally been the way to do
handle this. I don't remember the interfaces off the top of my head,
but I think you get an operand (which may be another reg, MEM, whatever)
and a register class. If you require an extra register to implement
that move, then you return the class you need and you'll get another
reg. Then you hack up your movXX or reload_* patterns to make use of it.
Yes, secondary reload has been set up to use scratch registers to expand
base addresses into address vectors since forever. Nothing significant
is changed there.
You can't tell which variety of address is in use just by looking at
the mode and address space by themselves (which is all we have in the
regular hook): it could be DImode or V64DImode. By looking at the
whole MEM we can see the whole picture. Actually all we need to see
is the mode of the address expression.
This is one of those cases were I think I'm missing something. If you
have the MEM, then you have the mode of the address, though perhaps not
the full computation of the address. And it looks like the address is
always Pmode on GCN. I must be mis-understanding your requirements.
For "global" and "flat" address spaces for scalar loads, or base
addresses for vectors, addresses are indeed Pmode (DImode).
For "lds" and "gds" address spaces addresses are SImode. (It's an
on-chip 64KiB low-latency memory.)
But, with the new patchset, addresses for *address vectors* are
V64DImode or V64SImode (or V32.., V16..., etc.).
Imagine two MEMs:
(mem:V64SI (reg:DI 123) AS0)
(mem:V64SI (reg:V64DI 123) AS0)
To base_address_mode, both are just "V64SI in address space 0"; they're
indistinguishable. But the first needs to be assigned to SGPR_REGS and
the second to VGPR_REGS.
Andrew
