gcc/ChangeLog:
* config/i386/x86-tune.def (X86_TUNE_FUSE_ALU_AND_BRANCH_MEM): Enable
for m_ZNVER6.
(X86_TUNE_FUSE_ALU_AND_BRANCH_MEM_IMM): Likewise.
(X86_TUNE_SSE_REDUCTION_PREFER_PSHUF): Likewise.
(cherry picked from commit ff3ae0cd90e5d6e9347c467ec8881781779171e2)
---
Bootstrap test passed.
Ok to backport to GCC 16.x after make -k check successful?
regards,
Venkat.
gcc/config/i386/x86-tune.def | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def
index fecca3bb777..d531bc8790e 100644
--- a/gcc/config/i386/x86-tune.def
+++ b/gcc/config/i386/x86-tune.def
@@ -161,12 +161,13 @@ DEF_TUNE (X86_TUNE_FUSE_MOV_AND_ALU, "fuse_mov_and_alu",
jump instruction when alu contains memory operand.
TODO: Not suported by TIGERLAKE and COPERLAKE, so m_CORE_AVX2 is wrong. */
DEF_TUNE (X86_TUNE_FUSE_ALU_AND_BRANCH_MEM, "fuse_alu_and_branch_mem",
- m_SANDYBRIDGE | m_CORE_AVX2 | m_ZHAOXIN | m_GENERIC | m_ZNVER3 |
m_ZNVER4 | m_ZNVER5)
+ m_SANDYBRIDGE | m_CORE_AVX2 | m_ZHAOXIN | m_GENERIC | m_ZNVER3
+ | m_ZNVER4 | m_ZNVER5 | m_ZNVER6)
/* X86_TUNE_FUSE_AND_BRANCH_MEM_IMM: Fuse alu with a subsequent conditional
jump instruction when alu contains both immediate and displacement. */
DEF_TUNE (X86_TUNE_FUSE_ALU_AND_BRANCH_MEM_IMM, "fuse_alu_and_branch_mem_imm",
- m_GENERIC | m_ZNVER4 | m_ZNVER5)
+ m_GENERIC | m_ZNVER4 | m_ZNVER5 | m_ZNVER6)
/* X86_TUNE_FUSE_AND_BRANCH_RIP_RELATIVE: Fuse alu with a subsequent
conditional jump instruction when alu contains IP relative address. */
@@ -604,8 +605,8 @@ DEF_TUNE (X86_TUNE_SSE_MOVCC_USE_BLENDV,
/* X86_TUNE_V4SI_REDUCTION_PREFER_SHUFD: Prefer pshuf to reduce V16QI,
V8HI, V8HI, V4SI, V4FI, V2DI modes when lshr are costlier. */
DEF_TUNE (X86_TUNE_SSE_REDUCTION_PREFER_PSHUF,
- "sse_reduction_prefer_pshuf", m_ZNVER4 | m_ZNVER5 | m_C86_4G_M7
- | m_C86_4G_M8)
+ "sse_reduction_prefer_pshuf", m_ZNVER4 | m_ZNVER5 | m_ZNVER6
+ | m_C86_4G_M7 | m_C86_4G_M8)
/*****************************************************************************/
/* AVX instruction selection tuning (some of SSE flags affects AVX, too) */
--
2.34.1
