LGTM.
> From: "Robin Dapp"<[email protected]>
> Date: Tue, Jun 16, 2026, 18:45
> Subject: [PATCH] RISC-V: Fix more scalar mode_idx instances [PR125478].
> To: "gcc-patches"<[email protected]>
> Cc: <[email protected]>, <[email protected]>, <[email protected]>,
> <[email protected]>, <[email protected]>
> Hi,
>
> This is another case of PR123022 and PR116149 where we query a scalar source
> operand instead of a vector operand, leading to a wrong AVL during avlprop.
>
> This patch moves viwalu, vfwalu, viwmul, and vfwmul to the proper
> bucket. I wonder why I didn't do that the last two times but it seems
> to be the correct choice now :)
>
> Regtested on rv64gcv_zvl512b and waiting for the CI.
>
> Regards
> Robin
>
> PR target/125478
>
> gcc/ChangeLog:
>
> * config/riscv/vector.md: Set widen-alu mode_idx to 3.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/pr125478.c: New test.
> ---
> gcc/config/riscv/vector.md | 16 +++----------
> .../gcc.target/riscv/rvv/autovec/pr125478.c | 23 +++++++++++++++++++
> 2 files changed, 26 insertions(+), 13 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr125478.c
>
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index fba631d670f..4f523f7c722 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -858,10 +858,10 @@ (define_attr "mode_idx" ""
> (const_int 2)
>
> (eq_attr "type"
> "vstux,vstox,vssegts,vssegtux,vssegtox,vfcvtftoi,vfwcvtitof,vfwcvtftoi,
> -
> vfwcvtftof,vmsfs,vired,viwred,vfredu,vfredo,vfwredu,vfwredo,vwsll")
> +
> vfwcvtftof,vmsfs,vired,viwred,vfredu,vfredo,vfwredu,vfwredo,vwsll,viwalu,vfwalu,viwmul,vfwmul")
> (const_int 3)
>
> - (eq_attr "type"
> "viwalu,viwmul,viwmuladd,vfwalu,vfwmul,vfwmuladd")
> + (eq_attr "type" "viwmuladd,vfwmuladd")
> (const_int 4)]
> (const_int INVALID_ATTRIBUTE)))
>
> @@ -4256,7 +4256,6 @@ (define_insn
> "@pred_single_widen_<plus_minus:optab><any_extend:su><mode>_scalar"
> "TARGET_VECTOR"
> "vw<plus_minus:insn><any_extend:u>.wx\t%0,%3,%z4%p1"
> [(set_attr "type" "vi<widen_binop_insn_type>")
> - (set_attr "mode_idx" "3")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
>
> (define_insn "@pred_single_widen_add<any_extend:su><mode>_extended_scalar"
> @@ -4279,7 +4278,6 @@ (define_insn
> "@pred_single_widen_add<any_extend:su><mode>_extended_scalar"
> "TARGET_VECTOR"
> "vwadd<any_extend:u>.wx\t%0,%3,%z4%p1"
> [(set_attr "type" "viwalu")
> - (set_attr "mode_idx" "3")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
>
> (define_insn "@pred_single_widen_sub<any_extend:su><mode>_extended_scalar"
> @@ -4302,7 +4300,6 @@ (define_insn
> "@pred_single_widen_sub<any_extend:su><mode>_extended_scalar"
> "TARGET_VECTOR"
> "vwsub<any_extend:u>.wx\t%0,%3,%z4%p1"
> [(set_attr "type" "viwalu")
> - (set_attr "mode_idx" "3")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
>
> (define_insn "@pred_widen_mulsu<mode>"
> @@ -4523,7 +4520,6 @@ (define_insn "@pred_<optab><mode>_scalar"
> "TARGET_VECTOR"
> "v<insn>.vx\t%0,%3,%4%p1"
> [(set_attr "type" "<int_binop_insn_type>")
> - (set_attr "mode_idx" "3")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "@pred_<optab><mode>_scalar"
> @@ -4545,7 +4541,6 @@ (define_insn "@pred_<optab><mode>_scalar"
> "TARGET_VECTOR"
> "v<insn>.vx\t%0,%3,%4%p1"
> [(set_attr "type" "<int_binop_insn_type>")
> - (set_attr "mode_idx" "3")
> (set_attr "mode" "<MODE>")])
>
> (define_expand "@pred_<optab><mode>_scalar"
> @@ -4600,7 +4595,6 @@ (define_insn "*pred_<optab><mode>_scalar"
> "TARGET_VECTOR"
> "v<insn>.vx\t%0,%3,%4%p1"
> [(set_attr "type" "<int_binop_insn_type>")
> - (set_attr "mode_idx" "3")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "*pred_<optab><mode>_extended_scalar"
> @@ -4623,7 +4617,6 @@ (define_insn "*pred_<optab><mode>_extended_scalar"
> "TARGET_VECTOR && !TARGET_64BIT"
> "v<insn>.vx\t%0,%3,%4%p1"
> [(set_attr "type" "<int_binop_insn_type>")
> - (set_attr "mode_idx" "3")
> (set_attr "mode" "<MODE>")])
>
> (define_expand "@pred_<optab><mode>_scalar"
> @@ -4678,7 +4671,6 @@ (define_insn "*pred_<optab><mode>_scalar"
> "TARGET_VECTOR"
> "v<insn>.vx\t%0,%3,%z4%p1"
> [(set_attr "type" "<int_binop_insn_type>")
> - (set_attr "mode_idx" "3")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "*pred_<optab><mode>_extended_scalar"
> @@ -4701,7 +4693,6 @@ (define_insn "*pred_<optab><mode>_extended_scalar"
> "TARGET_VECTOR && !TARGET_64BIT"
> "v<insn>.vx\t%0,%3,%z4%p1"
> [(set_attr "type" "<int_binop_insn_type>")
> - (set_attr "mode_idx" "3")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "@pred_<sat_op><mode>"
> @@ -4747,7 +4738,6 @@ (define_insn "@pred_<sat_op><mode>_scalar"
> "TARGET_VECTOR"
> "v<sat_op>.vx\t%0,%3,%z4%p1"
> [(set_attr "type" "<sat_insn_type>")
> - (set_attr "mode_idx" "3")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "@pred_<sat_op><mode>_scalar"
> @@ -7352,7 +7342,7 @@ (define_insn "@pred_dual_widen_<optab><mode>_scalar"
> [(set_attr "type" "vf<widen_binop_insn_type>")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")
> (set (attr "frm_mode")
> - (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
> + (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
>
> (define_insn "@pred_single_widen_add<mode>"
> [(set (match_operand:VWEXTF 0 "register_operand" "=&vr,
> &vr")
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr125478.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr125478.c
> new file mode 100644
> index 00000000000..46bccc594cd
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr125478.c
> @@ -0,0 +1,23 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-vector-bits=zvl
> -fdump-rtl-avlprop-details" } */
> +
> +long long a;
> +long b;
> +char c[169];
> +int d;
> +
> +int main() {
> + for (long g=0; g<13; ++g)
> + for (long h=0; h<13; ++h)
> + c[g*13 +h] = 8;
> +
> + for (unsigned g=0; g<13; g++)
> + for (int h=0; h<13; h +=3)
> + b += (c[g*13+h]) >> c[g*13 +9];
> +
> + a = (int)b;
> + if (a != 0)
> + __builtin_abort ();
> +}
> +
> +/* { dg-final { scan-rtl-dump-not "Propagating AVL: \\(const_int 1
> \\\[0x1\\\]\\)" "avlprop" } } */
> --
> 2.54.0
>
