On 15/06/2026 07:36, Artemiy Volkov wrote:
Hi Karl,
On Thu, Dec 11, 2025 at 01:31:19PM +0000, Karl Meakin wrote:
The comments for the "w", "x" and "y" register constraints in
gcc/config/aarch64/constraints.md were misleading. They apply to SVE
registers as well as Advanced SIMD and FP registers.
Just bear in mind that the comments say "SIMD" rather than "AdvSIMD", and
that SVE is also a SIMD technology. Thus, they can be interpreted as
stressing the fact that we use a unified set of registers for both of our
SIMD ISAs.
Thanks,
Artemiy
I would prefer to be explicit and remove any doubt.
gcc/ChangeLog:
* config/aarch64/constraints.md: Fix comments.
---
gcc/config/aarch64/constraints.md | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/gcc/config/aarch64/constraints.md
b/gcc/config/aarch64/constraints.md
index 7b9e5583bc7..b84993efb7f 100644
--- a/gcc/config/aarch64/constraints.md
+++ b/gcc/config/aarch64/constraints.md
@@ -40,20 +40,20 @@ (define_register_constraint "Ucr"
veneer.")
(define_register_constraint "w" "FP_REGS"
- "Floating point and SIMD vector registers.")
+ "SVE/NEON/FP registers, V0 - V31.")
(define_register_constraint "x" "FP_LO_REGS"
- "Floating point and SIMD vector registers V0 - V15.")
+ "SVE/NEON/FP registers, V0 - V15.")
(define_register_constraint "y" "FP_LO8_REGS"
- "Floating point and SIMD vector registers V0 - V7.")
+ "SVE/NEON/FP registers, V0 - V7.")
(define_register_constraint "Uw2" "FP_REGS"
- "Even floating point and SIMD vector registers."
+ "Even SVE/NEON/FP registers, V0, V2, ..., V30."
"regno % 2 == 0")
(define_register_constraint "Uw4" "FP_REGS"
- "4-tuple-aligned floating point and SIMD vector registers."
+ "4-tuple-aligned SVE/NEON/FP registers, V0, V4, ..., V28."
"regno % 4 == 0")
(define_register_constraint "Uwd" "FP_REGS"
--
2.43.0
