On 02/06/2026 19:49, Roger Sayle wrote:
>
> This patch provides improved (more accurate) RTX costs for -mthumb on ARM.
> My recent patch for double word multiplication, PR 122871, revealed that
> the current costs for THUMB code on ARM are... let's say a little dubious.
>
> To demonstrate the code generation improvements provided by better
> thumb1_rtx_costs consider the function below (from PR middle-end/122871).
>
> long long foo (long long a)
> {
> long long c = a << 33;
> c += a;
> return c;
> }
>
> With the ARM backend's current costs, this produces 11 instructions with
> -O2 -mthumb.
>
> Before: movs r3, r0
> movs r2, #0
> adds r2, r2, r0
> adcs r3, r3, r1
> adds r2, r2, r2
> adcs r3, r3, r3
> subs r2, r2, r0
> sbcs r3, r3, r1
> movs r0, r2
> movs r1, r3
> bx lr
>
> With sane RTX costs, GCC now generates the much more reasonable 5 insns:
>
> After: movs r2, #0
> lsls r3, r0, #1
> adds r0, r0, r2
> adcs r1, r1, r3
> bx lr
>
>
> Tested on arm-unknown-linux-gnueabihf with make bootstrap and make -k check
> with no new failures. I also noticed that arm.cc has a compiler warning
> when using GCC 11 as the host compiler; trivially silenced with a one line
> change. Ok for mainline?
>
>
> 2026-06-02 Roger Sayle <[email protected]>
>
> gcc/ChangeLog
> PR target/56102
> PR middle-end/122871
> * config/arm/arm.cc (thumb1_rtx_costs): Provide reasonable costs
> for PLUS, MINUS, COMPARE, AND, XOR, IOR, NEG, NOT, ASHIFT,
> ASHIFTRT and ROTATERT for SImode, DImode, HImode and QImode.
> (thumb1_size_rtx_costs): Likewise.
>
> (comp_not_to_clear_mask_str_un): Silence host compiler warning.
>
>
> Thanks in advance,
> Roger
> --
>
Thanks.
This is OK.
We could do a little better for DImode shifts by a constant >=32, since we know
in that case that we don't have to merge partial results from two sources. But
the code you've posted is still an improvement.
Eg:
uint64_t x;
x <<= 33;
becomes
LSLS Xhi, Xlo, #1
MOVS Xlo, #0
(2 insns instead of 4).
R.
