Kindly ping. Thanks a lot. Pan
-----Original Message----- From: Li, Pan2 <[email protected]> Sent: Tuesday, May 19, 2026 9:59 AM To: [email protected] Cc: [email protected]; [email protected]; [email protected]; [email protected]; Chen, Ken <[email protected]>; Liu, Hongtao <[email protected]>; [email protected]; [email protected]; Li, Pan2 <[email protected]> Subject: [PATCH v1 0/2] Implement unsigned scalar SAT_MUL form 11 From: Pan Li <[email protected]> This patch would like to try to match the the unsigned SAT_MUL form 11. The below test suites are passed for this patch: 1. The rv64gcv fully regression tests. 2. The x86 bootstrap tests. 3. The x86 fully regression tests. Pan Li (2): Match: Support unsigned scalar SAT_MUL form 11 RISC-V: Add testcase for unsigned scalar SAT_MUL form 11 gcc/match-sat-alu.pd | 11 ++++++++--- gcc/testsuite/gcc.target/riscv/sat/sat_arith.h | 15 +++++++++++++++ .../riscv/sat/sat_u_mul-12-u16-from-u128.c | 11 +++++++++++ .../riscv/sat/sat_u_mul-12-u16-from-u32.c | 11 +++++++++++ .../riscv/sat/sat_u_mul-12-u16-from-u64.rv32.c | 11 +++++++++++ .../riscv/sat/sat_u_mul-12-u16-from-u64.rv64.c | 11 +++++++++++ .../riscv/sat/sat_u_mul-12-u32-from-u128.c | 11 +++++++++++ .../riscv/sat/sat_u_mul-12-u32-from-u64.rv32.c | 11 +++++++++++ .../riscv/sat/sat_u_mul-12-u32-from-u64.rv64.c | 11 +++++++++++ .../riscv/sat/sat_u_mul-12-u64-from-u128.c | 11 +++++++++++ .../riscv/sat/sat_u_mul-12-u8-from-u128.c | 11 +++++++++++ .../riscv/sat/sat_u_mul-12-u8-from-u16.c | 11 +++++++++++ .../riscv/sat/sat_u_mul-12-u8-from-u32.c | 11 +++++++++++ .../riscv/sat/sat_u_mul-12-u8-from-u64.rv32.c | 11 +++++++++++ .../riscv/sat/sat_u_mul-12-u8-from-u64.rv64.c | 11 +++++++++++ .../riscv/sat/sat_u_mul-run-12-u16-from-u128.c | 16 ++++++++++++++++ .../riscv/sat/sat_u_mul-run-12-u16-from-u32.c | 16 ++++++++++++++++ .../riscv/sat/sat_u_mul-run-12-u16-from-u64.c | 16 ++++++++++++++++ .../riscv/sat/sat_u_mul-run-12-u32-from-u128.c | 16 ++++++++++++++++ .../riscv/sat/sat_u_mul-run-12-u32-from-u64.c | 16 ++++++++++++++++ .../riscv/sat/sat_u_mul-run-12-u64-from-u128.c | 16 ++++++++++++++++ .../riscv/sat/sat_u_mul-run-12-u8-from-u128.c | 16 ++++++++++++++++ .../riscv/sat/sat_u_mul-run-12-u8-from-u16.c | 16 ++++++++++++++++ .../riscv/sat/sat_u_mul-run-12-u8-from-u32.c | 16 ++++++++++++++++ .../riscv/sat/sat_u_mul-run-12-u8-from-u64.c | 16 ++++++++++++++++ 25 files changed, 326 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-12-u16-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-12-u16-from-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-12-u16-from-u64.rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-12-u16-from-u64.rv64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-12-u32-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-12-u32-from-u64.rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-12-u32-from-u64.rv64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-12-u64-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-12-u8-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-12-u8-from-u16.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-12-u8-from-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-12-u8-from-u64.rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-12-u8-from-u64.rv64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-12-u16-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-12-u16-from-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-12-u16-from-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-12-u32-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-12-u32-from-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-12-u64-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-12-u8-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-12-u8-from-u16.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-12-u8-from-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-12-u8-from-u64.c -- 2.43.0
