Hi gcc-patches mailing list, Karl Meakin via Sourceware Forge <[email protected]> has requested that the following forgejo pull request be published on the mailing list.
Created on: 2026-05-13 15:39:36+00:00 Latest update: 2026-05-27 12:55:37+00:00 Changes: 120 changed files, 20733 additions, 16797 deletions Head revision: karmea01/gcc-TEST ref dsg/karmea01/neon-port commit a20919e473475b5cd184e0f6c8a254ef9417f098 Base revision: gcc/gcc-TEST ref trunk commit 5caef7c4a904a065706ad375691f3b9d9bf525cb r17-626-g5caef7c4a904a0 Merge base: 5caef7c4a904a065706ad375691f3b9d9bf525cb Full diff url: https://forge.sourceware.org/gcc/gcc-TEST/pulls/158.diff Discussion: https://forge.sourceware.org/gcc/gcc-TEST/pulls/158 Requested Reviewers: rdfm, pinskia This patch is a proof of concept patch which ports a few NEON intrinsics (intrinsics defined in `arm_neon.h`) to the "pragma-based" framework used by SVE/SME intrinsics. If successful, I will follow up with further patches porting the rest. tested with `make check` changelog: * v1: Initial revision * v2: Appease `check_GNU_style.py` * v3: Drop unrelated `.editorconfig` changes which were included by mistake * v4: * Address review comments * Move reformatting of `config.gcc` into its own commit. * Merge `aarch64-neon-builtins.cc` into `aarch64-sve-builtins.cc` and rename it to `aarch64-acle-builtins.cc` * v5: Fix codegen for big-endian targets Changed files: - A: gcc/config/aarch64/aarch64-acle-builtins.cc - A: gcc/config/aarch64/aarch64-acle-builtins.h - A: gcc/config/aarch64/aarch64-neon-builtins-base.cc - A: gcc/config/aarch64/aarch64-neon-builtins-base.def - A: gcc/config/aarch64/aarch64-neon-builtins-base.h - A: gcc/config/aarch64/aarch64-neon-builtins-functions.h - A: gcc/config/aarch64/aarch64-neon-builtins-shapes.cc - A: gcc/config/aarch64/aarch64-neon-builtins-shapes.h - A: gcc/config/aarch64/aarch64-neon-builtins.cc - A: gcc/config/aarch64/aarch64-neon-builtins.def - A: gcc/config/aarch64/aarch64-neon-builtins.h - A: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopy_lane_indices.c - A: gcc/testsuite/gcc.target/aarch64/neon/aarch64-neon.exp - A: gcc/testsuite/gcc.target/aarch64/neon/arm_neon_test.h - A: gcc/testsuite/gcc.target/aarch64/neon/vadd.c - A: gcc/testsuite/gcc.target/aarch64/neon/vand.c - A: gcc/testsuite/gcc.target/aarch64/neon/vbcax.c - A: gcc/testsuite/gcc.target/aarch64/neon/vbic.c - A: gcc/testsuite/gcc.target/aarch64/neon/vbsl.c - A: gcc/testsuite/gcc.target/aarch64/neon/vcls.c - A: gcc/testsuite/gcc.target/aarch64/neon/vclz.c - A: gcc/testsuite/gcc.target/aarch64/neon/vcnt.c - A: gcc/testsuite/gcc.target/aarch64/neon/vcombine.c - A: gcc/testsuite/gcc.target/aarch64/neon/vcopy_lane.c - A: gcc/testsuite/gcc.target/aarch64/neon/vcreate.c - A: gcc/testsuite/gcc.target/aarch64/neon/vdup.c - A: gcc/testsuite/gcc.target/aarch64/neon/vdup_lane.c - A: gcc/testsuite/gcc.target/aarch64/neon/veor.c - A: gcc/testsuite/gcc.target/aarch64/neon/veor3.c - A: gcc/testsuite/gcc.target/aarch64/neon/vext.c - A: gcc/testsuite/gcc.target/aarch64/neon/vget_high.c - A: gcc/testsuite/gcc.target/aarch64/neon/vget_lane.c - A: gcc/testsuite/gcc.target/aarch64/neon/vget_low.c - A: gcc/testsuite/gcc.target/aarch64/neon/vmov_n.c - A: gcc/testsuite/gcc.target/aarch64/neon/vmvn.c - A: gcc/testsuite/gcc.target/aarch64/neon/vorn.c - A: gcc/testsuite/gcc.target/aarch64/neon/vorr.c - A: gcc/testsuite/gcc.target/aarch64/neon/vrax1.c - A: gcc/testsuite/gcc.target/aarch64/neon/vrbit.c - A: gcc/testsuite/gcc.target/aarch64/neon/vreinterpret.c - A: gcc/testsuite/gcc.target/aarch64/neon/vrev.c - A: gcc/testsuite/gcc.target/aarch64/neon/vset_lane.c - A: gcc/testsuite/gcc.target/aarch64/neon/vtrn.c - A: gcc/testsuite/gcc.target/aarch64/neon/vuzp.c - A: gcc/testsuite/gcc.target/aarch64/neon/vxar.c - A: gcc/testsuite/gcc.target/aarch64/neon/vzip.c - A: gcc/testsuite/gcc.target/aarch64/simd/vget_lane_indices.c - D: gcc/config/aarch64/aarch64-sve-builtins.cc - D: gcc/config/aarch64/aarch64-sve-builtins.h - D: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopy_lane_bf16_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopy_lane_bf16_indices_2.c - D: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopy_laneq_bf16_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopy_laneq_bf16_indices_2.c - D: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopyq_lane_bf16_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopyq_lane_bf16_indices_2.c - D: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopyq_laneq_bf16_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopyq_laneq_bf16_indices_2.c - D: gcc/testsuite/gcc.target/aarch64/simd/vget_lane_f32_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vget_lane_f64_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vget_lane_p16_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vget_lane_p8_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vget_lane_s16_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vget_lane_s32_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vget_lane_s64_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vget_lane_s8_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vget_lane_u16_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vget_lane_u32_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vget_lane_u64_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vget_lane_u8_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_f32_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_f64_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_p16_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_p8_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_s16_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_s32_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_s64_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_s8_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_u16_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_u32_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_u64_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_u8_indices_1.c - M: gcc/config.gcc - M: gcc/config/aarch64/aarch64-builtins.cc - M: gcc/config/aarch64/aarch64-builtins.h - M: gcc/config/aarch64/aarch64-c.cc - M: gcc/config/aarch64/aarch64-protos.h - M: gcc/config/aarch64/aarch64-simd-builtins.def - M: gcc/config/aarch64/aarch64-simd-pragma-builtins.def - M: gcc/config/aarch64/aarch64-simd.md - M: gcc/config/aarch64/aarch64-sve-builtins-base.cc - M: gcc/config/aarch64/aarch64-sve-builtins-base.h - M: gcc/config/aarch64/aarch64-sve-builtins-functions.h - M: gcc/config/aarch64/aarch64-sve-builtins-shapes.cc - M: gcc/config/aarch64/aarch64-sve-builtins-shapes.h - M: gcc/config/aarch64/aarch64-sve-builtins-sme.cc - M: gcc/config/aarch64/aarch64-sve-builtins-sme.h - M: gcc/config/aarch64/aarch64-sve-builtins-sve2.cc - M: gcc/config/aarch64/aarch64-sve-builtins-sve2.h - M: gcc/config/aarch64/aarch64-sve-builtins.def - M: gcc/config/aarch64/aarch64.cc - M: gcc/config/aarch64/aarch64.md - M: gcc/config/aarch64/arm_neon.h - M: gcc/config/aarch64/iterators.md - M: gcc/config/aarch64/t-aarch64 - M: gcc/testsuite/g++.target/aarch64/lane-bound-1.C - M: gcc/testsuite/g++.target/aarch64/pr103147-6.C - M: gcc/testsuite/g++.target/aarch64/pr117048.C - M: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bf16_dup.c - M: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bf16_vect_copy_lane_1.c - M: gcc/testsuite/gcc.target/aarch64/lane-bound-3.c - M: gcc/testsuite/gcc.target/aarch64/pr103147-6.c - M: gcc/testsuite/gcc.target/aarch64/pr113573.c - M: gcc/testsuite/gcc.target/aarch64/sha3_1.c - M: gcc/testsuite/gcc.target/aarch64/sha3_2.c - M: gcc/testsuite/gcc.target/aarch64/sha3_3.c - M: gcc/testsuite/gcc.target/aarch64/simd/fold_to_highpart_6.c - M: gcc/testsuite/gcc.target/aarch64/simd/mf8_data_2.c - M: gcc/testsuite/gcc.target/aarch64/simd/vset_lane_s16_const_1.c - M: gcc/testsuite/gcc.target/aarch64/sme/inlining_10.c - M: gcc/testsuite/gcc.target/aarch64/sme/inlining_11.c - M: gcc/testsuite/gcc.target/aarch64/target_attr_10.c - M: gcc/testsuite/gcc.target/aarch64/vmov_n_1.c Karl Meakin (7): aarch64: Reformat `config.gcc` aarch64: Rename `aarch64-sve-builtins` to `aarch64-acle-builtins` aarch64: Port NEON add intrinsics to pragma-based framework aarch64: Port NEON vector manipulation intrinsics to pragma-based framework aarch64: Port NEON bit manipulation intrinsics to pragma-based framework aarch64: Port NEON permutation intrinsics to pragma-based framework aarch64: Port NEON reinterpret intrinsics to pragma-based framework gcc/config.gcc | 41 +- ...e-builtins.cc => aarch64-acle-builtins.cc} | 955 +- ...sve-builtins.h => aarch64-acle-builtins.h} | 995 +- gcc/config/aarch64/aarch64-builtins.cc | 548 +- gcc/config/aarch64/aarch64-builtins.h | 1 + gcc/config/aarch64/aarch64-c.cc | 18 +- .../aarch64/aarch64-neon-builtins-base.cc | 799 + .../aarch64/aarch64-neon-builtins-base.def | 147 + .../aarch64/aarch64-neon-builtins-base.h | 29 + .../aarch64/aarch64-neon-builtins-functions.h | 29 + .../aarch64/aarch64-neon-builtins-shapes.cc | 132 + .../aarch64/aarch64-neon-builtins-shapes.h | 29 + gcc/config/aarch64/aarch64-neon-builtins.cc | 49 + gcc/config/aarch64/aarch64-neon-builtins.def | 40 + gcc/config/aarch64/aarch64-neon-builtins.h | 23 + gcc/config/aarch64/aarch64-protos.h | 5 +- gcc/config/aarch64/aarch64-simd-builtins.def | 36 - .../aarch64/aarch64-simd-pragma-builtins.def | 105 - gcc/config/aarch64/aarch64-simd.md | 8 +- .../aarch64/aarch64-sve-builtins-base.cc | 16 +- .../aarch64/aarch64-sve-builtins-base.h | 2 +- .../aarch64/aarch64-sve-builtins-functions.h | 2 +- .../aarch64/aarch64-sve-builtins-shapes.cc | 45 +- .../aarch64/aarch64-sve-builtins-shapes.h | 2 +- .../aarch64/aarch64-sve-builtins-sme.cc | 8 +- gcc/config/aarch64/aarch64-sve-builtins-sme.h | 2 +- .../aarch64/aarch64-sve-builtins-sve2.cc | 8 +- .../aarch64/aarch64-sve-builtins-sve2.h | 2 +- gcc/config/aarch64/aarch64-sve-builtins.def | 11 + gcc/config/aarch64/aarch64.cc | 40 +- gcc/config/aarch64/aarch64.md | 6 - gcc/config/aarch64/arm_neon.h | 22960 ++++++---------- gcc/config/aarch64/iterators.md | 2 +- gcc/config/aarch64/t-aarch64 | 43 +- .../g++.target/aarch64/lane-bound-1.C | 2 +- gcc/testsuite/g++.target/aarch64/pr103147-6.C | 1 + gcc/testsuite/g++.target/aarch64/pr117048.C | 2 +- .../aarch64/advsimd-intrinsics/bf16_dup.c | 7 +- .../bf16_vect_copy_lane_1.c | 3 +- .../vcopy_lane_bf16_indices_1.c | 18 - .../vcopy_lane_bf16_indices_2.c | 18 - .../advsimd-intrinsics/vcopy_lane_indices.c | 68 + .../vcopy_laneq_bf16_indices_1.c | 17 - .../vcopy_laneq_bf16_indices_2.c | 17 - .../vcopyq_lane_bf16_indices_1.c | 17 - .../vcopyq_lane_bf16_indices_2.c | 17 - .../vcopyq_laneq_bf16_indices_1.c | 17 - .../vcopyq_laneq_bf16_indices_2.c | 17 - .../gcc.target/aarch64/lane-bound-3.c | 4 +- .../gcc.target/aarch64/neon/aarch64-neon.exp | 43 + .../gcc.target/aarch64/neon/arm_neon_test.h | 24 + gcc/testsuite/gcc.target/aarch64/neon/vadd.c | 203 + gcc/testsuite/gcc.target/aarch64/neon/vand.c | 116 + gcc/testsuite/gcc.target/aarch64/neon/vbcax.c | 60 + gcc/testsuite/gcc.target/aarch64/neon/vbic.c | 116 + gcc/testsuite/gcc.target/aarch64/neon/vbsl.c | 214 + gcc/testsuite/gcc.target/aarch64/neon/vcls.c | 88 + gcc/testsuite/gcc.target/aarch64/neon/vclz.c | 88 + gcc/testsuite/gcc.target/aarch64/neon/vcnt.c | 25 + .../gcc.target/aarch64/neon/vcombine.c | 120 + .../gcc.target/aarch64/neon/vcopy_lane.c | 438 + .../gcc.target/aarch64/neon/vcreate.c | 119 + gcc/testsuite/gcc.target/aarch64/neon/vdup.c | 226 + .../gcc.target/aarch64/neon/vdup_lane.c | 647 + gcc/testsuite/gcc.target/aarch64/neon/veor.c | 116 + gcc/testsuite/gcc.target/aarch64/neon/veor3.c | 60 + gcc/testsuite/gcc.target/aarch64/neon/vext.c | 216 + .../gcc.target/aarch64/neon/vget_high.c | 116 + .../gcc.target/aarch64/neon/vget_lane.c | 449 + .../gcc.target/aarch64/neon/vget_low.c | 100 + .../gcc.target/aarch64/neon/vmov_n.c | 212 + gcc/testsuite/gcc.target/aarch64/neon/vmvn.c | 102 + gcc/testsuite/gcc.target/aarch64/neon/vorn.c | 116 + gcc/testsuite/gcc.target/aarch64/neon/vorr.c | 116 + gcc/testsuite/gcc.target/aarch64/neon/vrax1.c | 11 + gcc/testsuite/gcc.target/aarch64/neon/vrbit.c | 46 + .../gcc.target/aarch64/neon/vreinterpret.c | 3143 +++ gcc/testsuite/gcc.target/aarch64/neon/vrev.c | 311 + .../gcc.target/aarch64/neon/vset_lane.c | 234 + gcc/testsuite/gcc.target/aarch64/neon/vtrn.c | 566 + gcc/testsuite/gcc.target/aarch64/neon/vuzp.c | 566 + gcc/testsuite/gcc.target/aarch64/neon/vxar.c | 32 + gcc/testsuite/gcc.target/aarch64/neon/vzip.c | 559 + gcc/testsuite/gcc.target/aarch64/pr103147-6.c | 1 + gcc/testsuite/gcc.target/aarch64/pr113573.c | 62 +- gcc/testsuite/gcc.target/aarch64/sha3_1.c | 2 +- gcc/testsuite/gcc.target/aarch64/sha3_2.c | 2 +- gcc/testsuite/gcc.target/aarch64/sha3_3.c | 2 +- .../aarch64/simd/fold_to_highpart_6.c | 24 +- .../gcc.target/aarch64/simd/mf8_data_2.c | 1 - .../aarch64/simd/vget_lane_f32_indices_1.c | 17 - .../aarch64/simd/vget_lane_f64_indices_1.c | 17 - .../aarch64/simd/vget_lane_indices.c | 46 + .../aarch64/simd/vget_lane_p16_indices_1.c | 17 - .../aarch64/simd/vget_lane_p8_indices_1.c | 17 - .../aarch64/simd/vget_lane_s16_indices_1.c | 17 - .../aarch64/simd/vget_lane_s32_indices_1.c | 17 - .../aarch64/simd/vget_lane_s64_indices_1.c | 17 - .../aarch64/simd/vget_lane_s8_indices_1.c | 17 - .../aarch64/simd/vget_lane_u16_indices_1.c | 17 - .../aarch64/simd/vget_lane_u32_indices_1.c | 17 - .../aarch64/simd/vget_lane_u64_indices_1.c | 17 - .../aarch64/simd/vget_lane_u8_indices_1.c | 17 - .../aarch64/simd/vgetq_lane_f32_indices_1.c | 17 - .../aarch64/simd/vgetq_lane_f64_indices_1.c | 17 - .../aarch64/simd/vgetq_lane_p16_indices_1.c | 17 - .../aarch64/simd/vgetq_lane_p8_indices_1.c | 17 - .../aarch64/simd/vgetq_lane_s16_indices_1.c | 17 - .../aarch64/simd/vgetq_lane_s32_indices_1.c | 17 - .../aarch64/simd/vgetq_lane_s64_indices_1.c | 17 - .../aarch64/simd/vgetq_lane_s8_indices_1.c | 17 - .../aarch64/simd/vgetq_lane_u16_indices_1.c | 17 - .../aarch64/simd/vgetq_lane_u32_indices_1.c | 17 - .../aarch64/simd/vgetq_lane_u64_indices_1.c | 17 - .../aarch64/simd/vgetq_lane_u8_indices_1.c | 17 - .../aarch64/simd/vset_lane_s16_const_1.c | 2 +- .../gcc.target/aarch64/sme/inlining_10.c | 6 +- .../gcc.target/aarch64/sme/inlining_11.c | 7 +- .../gcc.target/aarch64/target_attr_10.c | 4 +- gcc/testsuite/gcc.target/aarch64/vmov_n_1.c | 2 +- 120 files changed, 20733 insertions(+), 16797 deletions(-) rename gcc/config/aarch64/{aarch64-sve-builtins.cc => aarch64-acle-builtins.cc} (87%) rename gcc/config/aarch64/{aarch64-sve-builtins.h => aarch64-acle-builtins.h} (59%) create mode 100644 gcc/config/aarch64/aarch64-neon-builtins-base.cc create mode 100644 gcc/config/aarch64/aarch64-neon-builtins-base.def create mode 100644 gcc/config/aarch64/aarch64-neon-builtins-base.h create mode 100644 gcc/config/aarch64/aarch64-neon-builtins-functions.h create mode 100644 gcc/config/aarch64/aarch64-neon-builtins-shapes.cc create mode 100644 gcc/config/aarch64/aarch64-neon-builtins-shapes.h create mode 100644 gcc/config/aarch64/aarch64-neon-builtins.cc create mode 100644 gcc/config/aarch64/aarch64-neon-builtins.def create mode 100644 gcc/config/aarch64/aarch64-neon-builtins.h delete mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopy_lane_bf16_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopy_lane_bf16_indices_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopy_lane_indices.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopy_laneq_bf16_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopy_laneq_bf16_indices_2.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopyq_lane_bf16_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopyq_lane_bf16_indices_2.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopyq_laneq_bf16_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopyq_laneq_bf16_indices_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/aarch64-neon.exp create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/arm_neon_test.h create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vadd.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vand.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vbcax.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vbic.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vbsl.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vcls.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vclz.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vcnt.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vcombine.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vcopy_lane.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vcreate.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vdup.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vdup_lane.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/veor.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/veor3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vext.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vget_high.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vget_lane.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vget_low.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vmov_n.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vmvn.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vorn.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vorr.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrax1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrbit.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vreinterpret.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrev.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vset_lane.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vtrn.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vuzp.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vxar.c create mode 100644 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100644 gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_u64_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_u8_indices_1.c Range-diff against v4: 1: 1410016e1ee8 = 1: 1410016e1ee8 aarch64: Reformat `config.gcc` 2: 42cce26efb4c = 2: 42cce26efb4c aarch64: Rename `aarch64-sve-builtins` to `aarch64-acle-builtins` 3: a731caf7d2cd ! 3: a68311b98751 aarch64: Port NEON add intrinsics to pragma-based framework @@ gcc/config/aarch64/aarch64-neon-builtins-base.cc (new) + auto arg1 = nargs >= 2 ? gimple_call_arg (f.call, 1) : nullptr; + auto arg2 = nargs >= 3 ? gimple_call_arg (f.call, 2) : nullptr; + -+ tree_code code; + auto type_class = f.type_suffix (0).tclass; + switch (type_class) + { + case TYPE_signed: + case TYPE_unsigned: -+ code = m_int_code; -+ break; ++ return gimple_build_assign (f.lhs, m_int_code, arg0, arg1, arg2); + case TYPE_float: -+ code = m_float_code; -+ break; ++ return gimple_build_assign (f.lhs, m_float_code, arg0, arg1, arg2); + case TYPE_poly: -+ code = m_poly_code; -+ break; ++ return gimple_build_assign (f.lhs, m_poly_code, arg0, arg1, arg2); + default: + gcc_unreachable (); + } -+ -+ return gimple_build_assign (f.lhs, code, arg0, arg1, arg2); + } +}; + 4: 6f4dee3db40f ! 4: 2359419106db aarch64: Port NEON vector manipulation intrinsics to pragma-based framework @@ gcc/config/aarch64/aarch64-neon-builtins-base.cc using namespace aarch64_acle; ++/* Convert a lane index to the correct index for the target endianness. ++ For little-endian targets, this is a no-op. ++ For big-endian targets, this is `len - index - 1`. */ ++tree ++convert_lane_index (poly_uint64 len, tree index) ++{ ++ auto index_type = TREE_TYPE (index); ++ return !BYTES_BIG_ENDIAN ++ ? index ++ : fold_build2 (MINUS_EXPR, index_type, ++ fold_build2 (MINUS_EXPR, index_type, ++ build_int_cst_type (index_type, len), ++ index), ++ build_one_cst (index_type)); ++} ++ +/* Build a `VEC[INDEX]` expression. */ +tree +build_lane_get (tree vec, tree index) +{ + auto vec_type = TREE_TYPE (vec); ++ auto vec_len = TYPE_VECTOR_SUBPARTS (vec_type); + auto elem_type = TREE_TYPE (vec_type); + auto elem_size = TYPE_SIZE (elem_type); -+ auto offset = fold_build2 (MULT_EXPR, bitsizetype, elem_size, index); ++ auto offset = fold_build2 (MULT_EXPR, bitsizetype, elem_size, ++ convert_lane_index (vec_len, index)); + return fold_build3 (BIT_FIELD_REF, elem_type, vec, elem_size, offset); +} + @@ gcc/config/aarch64/aarch64-neon-builtins-base.cc +build_lane_set (tree vec, tree index, tree elem) +{ + auto vec_type = TREE_TYPE (vec); ++ auto vec_len = TYPE_VECTOR_SUBPARTS (vec_type); + auto elem_type = TREE_TYPE (vec_type); + auto elem_size = TYPE_SIZE (elem_type); -+ auto offset = fold_build2 (MULT_EXPR, bitsizetype, elem_size, index); ++ auto offset = fold_build2 (MULT_EXPR, bitsizetype, elem_size, ++ convert_lane_index (vec_len, index)); + return fold_build3 (BIT_INSERT_EXPR, vec_type, vec, elem, offset); +} + @@ gcc/config/aarch64/aarch64-neon-builtins-base.cc: public: + arg2 = f.force_val (fold_build1 (VIEW_CONVERT_EXPR, elem_type, arg2)); + } + ++ if (BYTES_BIG_ENDIAN) ++ std::swap (arg1, arg2); ++ + return gimple_build_assign (f.lhs, + build_constructor_va (ret_type, 2, NULL_TREE, + arg1, NULL_TREE, arg2)); @@ gcc/config/aarch64/aarch64-neon-builtins-base.cc: public: + auto src = gimple_call_arg (f.call, 0); + auto half + = fold_build3 (BIT_FIELD_REF, TREE_TYPE (f.lhs), src, bitsize_int (64), -+ bitsize_int (high_half_p ? 64 : 0)); ++ bitsize_int (high_half_p ^ BYTES_BIG_ENDIAN ? 64 : 0)); + return gimple_build_assign (f.lhs, half); + } +}; @@ gcc/testsuite/gcc.target/aarch64/lane-bound-3.c __builtin_unreachable(); } + ## gcc/testsuite/gcc.target/aarch64/neon/aarch64-neon.exp ## +@@ gcc/testsuite/gcc.target/aarch64/neon/aarch64-neon.exp: dg-init + dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*\[cCs\]]] \ + " -ansi -pedantic-errors -std=c23 -O3 -march=armv8-a+simd" "" + ++# Again, for big-endian targets. ++dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*\[cCs\]]] \ ++ " -ansi -pedantic-errors -std=c23 -O3 -march=armv8-a+simd -mbig-endian" "" ++ + # All done. + dg-finish + ## gcc/testsuite/gcc.target/aarch64/neon/arm_neon_test.h ## @@ @@ gcc/testsuite/gcc.target/aarch64/neon/vcopy_lane.c (new) +*/ +TEST_COPY_LANE (vcopyq_laneq_u16, uint16x8_t, uint16x8_t) + ++// FIXME: these functions generate suboptimal code on big-endian: ++// ins v1.s[0], v0.s[0] ++// mov v0.16b, v1.16b ++// ret ++ +/* -+** test_vcopy_lane_f32: ++** test_vcopy_lane_f32: { xfail { aarch64_big_endian || { any-opts mbig-endian" } } } +** ins v0\.s\[1\], v1\.s\[1\] +** ret +*/ +TEST_COPY_LANE (vcopy_lane_f32, float32x2_t, float32x2_t) + +/* -+** test_vcopy_lane_s32: ++** test_vcopy_lane_s32: { xfail { aarch64_big_endian || { any-opts mbig-endian" } } } +** ins v0\.s\[1\], v1\.s\[1\] +** ret +*/ +TEST_COPY_LANE (vcopy_lane_s32, int32x2_t, int32x2_t) + +/* -+** test_vcopy_lane_u32: ++** test_vcopy_lane_u32: { xfail { aarch64_big_endian || { any-opts mbig-endian" } } } +** ins v0\.s\[1\], v1\.s\[1\] +** ret +*/ @@ gcc/testsuite/gcc.target/aarch64/neon/vcopy_lane.c (new) +*/ +TEST_COPY_LANE (vcopyq_lane_u64, uint64x2_t, uint64x1_t) + ++// FIXME: these functions generate suboptimal code on big-endian: ++// ins v1.d[0], v0.d[0] ++// mov v0.16b, v1.16b ++// ret ++ +/* -+** test_vcopyq_laneq_f64: ++** test_vcopyq_laneq_f64: { xfail { aarch64_big_endian || { any-opts "-mbig-endian" } } } +** ins v0\.d\[1\], v1\.d\[1\] +** ret +*/ +TEST_COPY_LANE (vcopyq_laneq_f64, float64x2_t, float64x2_t) + +/* -+** test_vcopyq_laneq_p64: ++** test_vcopyq_laneq_p64: { xfail { aarch64_big_endian || { any-opts "-mbig-endian" } } } +** ins v0\.d\[1\], v1\.d\[1\] +** ret +*/ +TEST_COPY_LANE (vcopyq_laneq_p64, poly64x2_t, poly64x2_t) + +/* -+** test_vcopyq_laneq_s64: ++** test_vcopyq_laneq_s64: { xfail { aarch64_big_endian || { any-opts "-mbig-endian" } } } +** ins v0\.d\[1\], v1\.d\[1\] +** ret +*/ +TEST_COPY_LANE (vcopyq_laneq_s64, int64x2_t, int64x2_t) + +/* -+** test_vcopyq_laneq_u64: ++** test_vcopyq_laneq_u64: { xfail { aarch64_big_endian || { any-opts "-mbig-endian" } } } +** ins v0\.d\[1\], v1\.d\[1\] +** ret +*/ @@ gcc/testsuite/gcc.target/aarch64/neon/vget_lane.c (new) + +#include "arm_neon_test.h" + -+#define TEST_GET_LANE(NAME, RET_TYPE, ARG_TYPE) \ -+ RET_TYPE test_##NAME (ARG_TYPE arg1) \ ++#define TEST_GET_FIRST_LANE(NAME, RET_TYPE, ARG_TYPE) \ ++ RET_TYPE test_##NAME##_first (ARG_TYPE arg1) { return NAME (arg1, 0); } ++ ++#define TEST_GET_LAST_LANE(NAME, RET_TYPE, ARG_TYPE) \ ++ RET_TYPE test_##NAME##_last (ARG_TYPE arg1) \ + { \ + return NAME (arg1, VEC_LEN (arg1) - 1); \ + } + +/* -+** test_vget_lane_u8: ++** test_vget_lane_u8_first: ++** umov w0, v0\.b\[0\] ++** ret ++*/ ++TEST_GET_FIRST_LANE (vget_lane_u8, uint8_t, uint8x8_t) ++ ++/* ++** test_vget_lane_s8_first: ++** umov w0, v0\.b\[0\] ++** ret ++*/ ++TEST_GET_FIRST_LANE (vget_lane_s8, int8_t, int8x8_t) ++ ++/* ++** test_vget_lane_p8_first: ++** umov w0, v0\.b\[0\] ++** ret ++*/ ++TEST_GET_FIRST_LANE (vget_lane_p8, poly8_t, poly8x8_t) ++ ++/* ++** test_vget_lane_mf8_first: ++** ret ++*/ ++TEST_GET_FIRST_LANE (vget_lane_mf8, mfloat8_t, mfloat8x8_t) ++ ++/* ++** test_vgetq_lane_u8_first: ++** umov w0, v0\.b\[0\] ++** ret ++*/ ++TEST_GET_FIRST_LANE (vgetq_lane_u8, uint8_t, uint8x16_t) ++ ++/* ++** test_vgetq_lane_s8_first: ++** umov w0, v0\.b\[0\] ++** ret ++*/ ++TEST_GET_FIRST_LANE (vgetq_lane_s8, int8_t, int8x16_t) ++ ++/* ++** test_vgetq_lane_p8_first: ++** umov w0, v0\.b\[0\] ++** ret ++*/ ++TEST_GET_FIRST_LANE (vgetq_lane_p8, poly8_t, poly8x16_t) ++ ++/* ++** test_vgetq_lane_mf8_first: ++** ret ++*/ ++TEST_GET_FIRST_LANE (vgetq_lane_mf8, mfloat8_t, mfloat8x16_t) ++ ++/* ++** test_vget_lane_u16_first: ++** umov w0, v0\.h\[0\] ++** ret ++*/ ++TEST_GET_FIRST_LANE (vget_lane_u16, uint16_t, uint16x4_t) ++ ++/* ++** test_vget_lane_s16_first: ++** umov w0, v0\.h\[0\] ++** ret ++*/ ++TEST_GET_FIRST_LANE (vget_lane_s16, int16_t, int16x4_t) ++ ++/* ++** test_vget_lane_p16_first: ++** umov w0, v0\.h\[0\] ++** ret ++*/ ++TEST_GET_FIRST_LANE (vget_lane_p16, poly16_t, poly16x4_t) ++ ++/* ++** test_vget_lane_f16_first: ++** ret ++*/ ++TEST_GET_FIRST_LANE (vget_lane_f16, float16_t, float16x4_t) ++ ++/* ++** test_vget_lane_bf16_first: ++** ret ++*/ ++TEST_GET_FIRST_LANE (vget_lane_bf16, bfloat16_t, bfloat16x4_t) ++ ++/* ++** test_vgetq_lane_u16_first: ++** umov w0, v0\.h\[0\] ++** ret ++*/ ++TEST_GET_FIRST_LANE (vgetq_lane_u16, uint16_t, uint16x8_t) ++ ++/* ++** test_vgetq_lane_s16_first: ++** umov w0, v0\.h\[0\] ++** ret ++*/ ++TEST_GET_FIRST_LANE (vgetq_lane_s16, int16_t, int16x8_t) ++ ++/* ++** test_vgetq_lane_p16_first: ++** umov w0, v0\.h\[0\] ++** ret ++*/ ++TEST_GET_FIRST_LANE (vgetq_lane_p16, poly16_t, poly16x8_t) ++ ++/* ++** test_vgetq_lane_f16_first: ++** ret ++*/ ++TEST_GET_FIRST_LANE (vgetq_lane_f16, float16_t, float16x8_t) ++ ++/* ++** test_vgetq_lane_bf16_first: ++** ret ++*/ ++TEST_GET_FIRST_LANE (vgetq_lane_bf16, bfloat16_t, bfloat16x8_t) ++ ++/* ++** test_vget_lane_u32_first: ++** fmov w0, s0 ++** ret ++*/ ++TEST_GET_FIRST_LANE (vget_lane_u32, uint32_t, uint32x2_t) ++ ++/* ++** test_vget_lane_s32_first: ++** fmov w0, s0 ++** ret ++*/ ++TEST_GET_FIRST_LANE (vget_lane_s32, int32_t, int32x2_t) ++ ++/* ++** test_vget_lane_f32_first: ++** ret ++*/ ++TEST_GET_FIRST_LANE (vget_lane_f32, float32_t, float32x2_t) ++ ++/* ++** test_vgetq_lane_u32_first: ++** fmov w0, s0 ++** ret ++*/ ++TEST_GET_FIRST_LANE (vgetq_lane_u32, uint32_t, uint32x4_t) ++ ++/* ++** test_vgetq_lane_s32_first: ++** fmov w0, s0 ++** ret ++*/ ++TEST_GET_FIRST_LANE (vgetq_lane_s32, int32_t, int32x4_t) ++ ++/* ++** test_vgetq_lane_f32_first: ++** ret ++*/ ++TEST_GET_FIRST_LANE (vgetq_lane_f32, float32_t, float32x4_t) ++ ++/* ++** test_vget_lane_u64_first: ++** fmov x0, d0 ++** ret ++*/ ++TEST_GET_FIRST_LANE (vget_lane_u64, uint64_t, uint64x1_t) ++ ++/* ++** test_vget_lane_s64_first: ++** fmov x0, d0 ++** ret ++*/ ++TEST_GET_FIRST_LANE (vget_lane_s64, int64_t, int64x1_t) ++ ++/* ++** test_vget_lane_p64_first: ++** fmov x0, d0 ++** ret ++*/ ++TEST_GET_FIRST_LANE (vget_lane_p64, poly64_t, poly64x1_t) ++ ++/* ++** test_vget_lane_f64_first: ++** ret ++*/ ++TEST_GET_FIRST_LANE (vget_lane_f64, float64_t, float64x1_t) ++ ++/* ++** test_vgetq_lane_u64_first: ++** fmov x0, d0 ++** ret ++*/ ++TEST_GET_FIRST_LANE (vgetq_lane_u64, uint64_t, uint64x2_t) ++ ++/* ++** test_vgetq_lane_s64_first: ++** fmov x0, d0 ++** ret ++*/ ++TEST_GET_FIRST_LANE (vgetq_lane_s64, int64_t, int64x2_t) ++ ++/* ++** test_vgetq_lane_p64_first: ++** fmov x0, d0 ++** ret ++*/ ++TEST_GET_FIRST_LANE (vgetq_lane_p64, poly64_t, poly64x2_t) ++ ++/* ++** test_vgetq_lane_f64_first: ++** ret ++*/ ++TEST_GET_FIRST_LANE (vgetq_lane_f64, float64_t, float64x2_t) ++ ++/* ++** test_vget_lane_u8_last: +** umov w0, v0\.b\[7\] +** ret +*/ -+TEST_GET_LANE (vget_lane_u8, uint8_t, uint8x8_t) ++TEST_GET_LAST_LANE (vget_lane_u8, uint8_t, uint8x8_t) + +/* -+** test_vget_lane_s8: ++** test_vget_lane_s8_last: +** umov w0, v0\.b\[7\] +** ret +*/ -+TEST_GET_LANE (vget_lane_s8, int8_t, int8x8_t) ++TEST_GET_LAST_LANE (vget_lane_s8, int8_t, int8x8_t) + +/* -+** test_vget_lane_p8: ++** test_vget_lane_p8_last: +** umov w0, v0\.b\[7\] +** ret +*/ -+TEST_GET_LANE (vget_lane_p8, poly8_t, poly8x8_t) ++TEST_GET_LAST_LANE (vget_lane_p8, poly8_t, poly8x8_t) + +/* -+** test_vget_lane_mf8: ++** test_vget_lane_mf8_last: +** dup b0, v0\.b\[7\] +** ret +*/ -+TEST_GET_LANE (vget_lane_mf8, mfloat8_t, mfloat8x8_t) ++TEST_GET_LAST_LANE (vget_lane_mf8, mfloat8_t, mfloat8x8_t) + +/* -+** test_vgetq_lane_u8: ++** test_vgetq_lane_u8_last: +** umov w0, v0\.b\[15\] +** ret +*/ -+TEST_GET_LANE (vgetq_lane_u8, uint8_t, uint8x16_t) ++TEST_GET_LAST_LANE (vgetq_lane_u8, uint8_t, uint8x16_t) + +/* -+** test_vgetq_lane_s8: ++** test_vgetq_lane_s8_last: +** umov w0, v0\.b\[15\] +** ret +*/ -+TEST_GET_LANE (vgetq_lane_s8, int8_t, int8x16_t) ++TEST_GET_LAST_LANE (vgetq_lane_s8, int8_t, int8x16_t) + +/* -+** test_vgetq_lane_p8: ++** test_vgetq_lane_p8_last: +** umov w0, v0\.b\[15\] +** ret +*/ -+TEST_GET_LANE (vgetq_lane_p8, poly8_t, poly8x16_t) ++TEST_GET_LAST_LANE (vgetq_lane_p8, poly8_t, poly8x16_t) + +/* -+** test_vgetq_lane_mf8: ++** test_vgetq_lane_mf8_last: +** dup b0, v0\.b\[15\] +** ret +*/ -+TEST_GET_LANE (vgetq_lane_mf8, mfloat8_t, mfloat8x16_t) ++TEST_GET_LAST_LANE (vgetq_lane_mf8, mfloat8_t, mfloat8x16_t) + +/* -+** test_vget_lane_u16: ++** test_vget_lane_u16_last: +** umov w0, v0\.h\[3\] +** ret +*/ -+TEST_GET_LANE (vget_lane_u16, uint16_t, uint16x4_t) ++TEST_GET_LAST_LANE (vget_lane_u16, uint16_t, uint16x4_t) + +/* -+** test_vget_lane_s16: ++** test_vget_lane_s16_last: +** umov w0, v0\.h\[3\] +** ret +*/ -+TEST_GET_LANE (vget_lane_s16, int16_t, int16x4_t) ++TEST_GET_LAST_LANE (vget_lane_s16, int16_t, int16x4_t) + +/* -+** test_vget_lane_p16: ++** test_vget_lane_p16_last: +** umov w0, v0\.h\[3\] +** ret +*/ -+TEST_GET_LANE (vget_lane_p16, poly16_t, poly16x4_t) ++TEST_GET_LAST_LANE (vget_lane_p16, poly16_t, poly16x4_t) + +/* -+** test_vget_lane_f16: ++** test_vget_lane_f16_last: +** dup h0, v0\.h\[3\] +** ret +*/ -+TEST_GET_LANE (vget_lane_f16, float16_t, float16x4_t) ++TEST_GET_LAST_LANE (vget_lane_f16, float16_t, float16x4_t) + +/* -+** test_vget_lane_bf16: ++** test_vget_lane_bf16_last: +** dup h0, v0\.h\[3\] +** ret +*/ -+TEST_GET_LANE (vget_lane_bf16, bfloat16_t, bfloat16x4_t) ++TEST_GET_LAST_LANE (vget_lane_bf16, bfloat16_t, bfloat16x4_t) + +/* -+** test_vgetq_lane_u16: ++** test_vgetq_lane_u16_last: +** umov w0, v0\.h\[7\] +** ret +*/ -+TEST_GET_LANE (vgetq_lane_u16, uint16_t, uint16x8_t) ++TEST_GET_LAST_LANE (vgetq_lane_u16, uint16_t, uint16x8_t) + +/* -+** test_vgetq_lane_s16: ++** test_vgetq_lane_s16_last: +** umov w0, v0\.h\[7\] +** ret +*/ -+TEST_GET_LANE (vgetq_lane_s16, int16_t, int16x8_t) ++TEST_GET_LAST_LANE (vgetq_lane_s16, int16_t, int16x8_t) + +/* -+** test_vgetq_lane_p16: ++** test_vgetq_lane_p16_last: +** umov w0, v0\.h\[7\] +** ret +*/ -+TEST_GET_LANE (vgetq_lane_p16, poly16_t, poly16x8_t) ++TEST_GET_LAST_LANE (vgetq_lane_p16, poly16_t, poly16x8_t) + +/* -+** test_vgetq_lane_f16: ++** test_vgetq_lane_f16_last: +** dup h0, v0\.h\[7\] +** ret +*/ -+TEST_GET_LANE (vgetq_lane_f16, float16_t, float16x8_t) ++TEST_GET_LAST_LANE (vgetq_lane_f16, float16_t, float16x8_t) + +/* -+** test_vgetq_lane_bf16: ++** test_vgetq_lane_bf16_last: +** dup h0, v0\.h\[7\] +** ret +*/ -+TEST_GET_LANE (vgetq_lane_bf16, bfloat16_t, bfloat16x8_t) ++TEST_GET_LAST_LANE (vgetq_lane_bf16, bfloat16_t, bfloat16x8_t) + +/* -+** test_vget_lane_u32: ++** test_vget_lane_u32_last: +** umov w0, v0\.s\[1\] +** ret +*/ -+TEST_GET_LANE (vget_lane_u32, uint32_t, uint32x2_t) ++TEST_GET_LAST_LANE (vget_lane_u32, uint32_t, uint32x2_t) + +/* -+** test_vget_lane_s32: ++** test_vget_lane_s32_last: +** umov w0, v0\.s\[1\] +** ret +*/ -+TEST_GET_LANE (vget_lane_s32, int32_t, int32x2_t) ++TEST_GET_LAST_LANE (vget_lane_s32, int32_t, int32x2_t) + +/* -+** test_vget_lane_f32: ++** test_vget_lane_f32_last: +** dup s0, v0\.s\[1\] +** ret +*/ -+TEST_GET_LANE (vget_lane_f32, float32_t, float32x2_t) ++TEST_GET_LAST_LANE (vget_lane_f32, float32_t, float32x2_t) + +/* -+** test_vgetq_lane_u32: ++** test_vgetq_lane_u32_last: +** umov w0, v0\.s\[3\] +** ret +*/ -+TEST_GET_LANE (vgetq_lane_u32, uint32_t, uint32x4_t) ++TEST_GET_LAST_LANE (vgetq_lane_u32, uint32_t, uint32x4_t) + +/* -+** test_vgetq_lane_s32: ++** test_vgetq_lane_s32_last: +** umov w0, v0\.s\[3\] +** ret +*/ -+TEST_GET_LANE (vgetq_lane_s32, int32_t, int32x4_t) ++TEST_GET_LAST_LANE (vgetq_lane_s32, int32_t, int32x4_t) + +/* -+** test_vgetq_lane_f32: ++** test_vgetq_lane_f32_last: +** dup s0, v0\.s\[3\] +** ret +*/ -+TEST_GET_LANE (vgetq_lane_f32, float32_t, float32x4_t) ++TEST_GET_LAST_LANE (vgetq_lane_f32, float32_t, float32x4_t) + +/* -+** test_vget_lane_u64: ++** test_vget_lane_u64_last: +** fmov x0, d0 +** ret +*/ -+TEST_GET_LANE (vget_lane_u64, uint64_t, uint64x1_t) ++TEST_GET_LAST_LANE (vget_lane_u64, uint64_t, uint64x1_t) + +/* -+** test_vget_lane_s64: ++** test_vget_lane_s64_last: +** fmov x0, d0 +** ret +*/ -+TEST_GET_LANE (vget_lane_s64, int64_t, int64x1_t) ++TEST_GET_LAST_LANE (vget_lane_s64, int64_t, int64x1_t) + +/* -+** test_vget_lane_p64: ++** test_vget_lane_p64_last: +** fmov x0, d0 +** ret +*/ -+TEST_GET_LANE (vget_lane_p64, poly64_t, poly64x1_t) ++TEST_GET_LAST_LANE (vget_lane_p64, poly64_t, poly64x1_t) + +/* -+** test_vget_lane_f64: ++** test_vget_lane_f64_last: +** ret +*/ -+TEST_GET_LANE (vget_lane_f64, float64_t, float64x1_t) ++TEST_GET_LAST_LANE (vget_lane_f64, float64_t, float64x1_t) +/* -+** test_vgetq_lane_u64: ++** test_vgetq_lane_u64_last: +** umov x0, v0\.d\[1\] +** ret +*/ -+TEST_GET_LANE (vgetq_lane_u64, uint64_t, uint64x2_t) ++TEST_GET_LAST_LANE (vgetq_lane_u64, uint64_t, uint64x2_t) + +/* -+** test_vgetq_lane_s64: ++** test_vgetq_lane_s64_last: +** umov x0, v0\.d\[1\] +** ret +*/ -+TEST_GET_LANE (vgetq_lane_s64, int64_t, int64x2_t) ++TEST_GET_LAST_LANE (vgetq_lane_s64, int64_t, int64x2_t) + +/* -+** test_vgetq_lane_p64: ++** test_vgetq_lane_p64_last: +** umov x0, v0\.d\[1\] +** ret +*/ -+TEST_GET_LANE (vgetq_lane_p64, poly64_t, poly64x2_t) ++TEST_GET_LAST_LANE (vgetq_lane_p64, poly64_t, poly64x2_t) + +/* -+** test_vgetq_lane_f64: ++** test_vgetq_lane_f64_last: +** dup d0, v0\.d\[1\] +** ret +*/ -+TEST_GET_LANE (vgetq_lane_f64, float64_t, float64x2_t) ++TEST_GET_LAST_LANE (vgetq_lane_f64, float64_t, float64x2_t) ## gcc/testsuite/gcc.target/aarch64/neon/vget_low.c (new) ## @@ 5: b0ae3a064bf0 ! 5: 75dcf7bfce80 aarch64: Port NEON bit manipulation intrinsics to pragma-based framework @@ gcc/config/aarch64/aarch64-neon-builtins-base.cc + : expr; +} + - /* Build a `VEC[INDEX]` expression. */ - tree - build_lane_get (tree vec, tree index) + /* Convert a lane index to the correct index for the target endianness. + For little-endian targets, this is a no-op. + For big-endian targets, this is `len - index - 1`. */ @@ gcc/config/aarch64/aarch64-neon-builtins-base.cc: struct gimple_dup_lane : public gimple_function_base } }; @@ gcc/config/aarch64/aarch64-neon-builtins-base.cc: struct gimple_dup_lane : publi + } +}; + -+/* RAX1 (n, m) = n ^ rotl (m, 1). */ ++/* RAX1 (n, m) = n ^ rotl (m, splat (1)). */ +class gimple_rax1 : public gimple_function_base +{ +public: 6: aae4af02f5d5 ! 6: c6fb10d719c6 aarch64: Port NEON permutation intrinsics to pragma-based framework @@ gcc/config/aarch64/aarch64-neon-builtins-base.cc: public: + auto b + = gimple_call_num_args (f.call) >= 2 ? gimple_call_arg (f.call, 1) : a; + ++ if (BYTES_BIG_ENDIAN) ++ std::swap (a, b); ++ + auto mask = this->m_mask_fn (f); + return gimple_build_assign (f.lhs, VEC_PERM_EXPR, a, b, mask); + } @@ gcc/config/aarch64/aarch64-neon-builtins-base.cc: public: + auto a = gimple_call_arg (f.call, 0); + auto b = gimple_call_arg (f.call, 1); + ++ if (BYTES_BIG_ENDIAN) ++ std::swap (a, b); ++ + auto arg_type = TREE_TYPE (a); + gcc_assert (arg_type == TREE_TYPE (b)); + @@ gcc/config/aarch64/aarch64-neon-builtins-base.cc: public: +{ + auto vec_type = TREE_TYPE (gimple_call_arg (f.call, 0)); + auto start = int_cst_value (gimple_call_arg (f.call, 2)); -+ auto len = TYPE_VECTOR_SUBPARTS (vec_type); ++ auto len = TYPE_VECTOR_SUBPARTS (vec_type).to_constant (); + auto mask_type = build_vector_type (sizetype, len); -+ return build_vec_series (mask_type, size_int (start), size_int (1)); ++ return build_vec_series (mask_type, ++ size_int (!BYTES_BIG_ENDIAN ? start : len - start), ++ size_int (1)); +} + +/* vrev16_u8 => {{1, 0}, {3, 2}, {5, 4}, {7, 6}} @@ gcc/config/aarch64/aarch64-neon-builtins-base.cc: public: + rev64_u32 => {{1, 0}} + rev64q_u32 => {{1, 0}, {3, 2}} +*/ -+ +template <unsigned int bits_per_word> +tree +rev_mask (gimple_folder &f) @@ gcc/config/aarch64/aarch64-neon-builtins-base.cc: public: + + for (auto i = 0U; i < len / 2; i++) + { -+ builder.quick_push (size_int (i * 2 + secondary_p)); -+ builder.quick_push (size_int (len + i * 2 + secondary_p)); ++ builder.quick_push (size_int (i * 2 + (secondary_p ^ BYTES_BIG_ENDIAN))); ++ builder.quick_push ( ++ size_int (len + i * 2 + (secondary_p ^ BYTES_BIG_ENDIAN))); + } + + return builder.build (); @@ gcc/config/aarch64/aarch64-neon-builtins-base.cc: public: + auto vec_type = TREE_TYPE (gimple_call_arg (f.call, 0)); + auto len = TYPE_VECTOR_SUBPARTS (vec_type).to_constant (); + auto mask_type = build_vector_type (sizetype, len); -+ return build_vec_series (mask_type, size_int (secondary_p), size_int (2)); ++ return build_vec_series (mask_type, size_int (secondary_p ^ BYTES_BIG_ENDIAN), ++ size_int (2)); +} + +/* ZIP1 ({a0, a1}, {b0, b1}) = {a0, b0} @@ gcc/config/aarch64/aarch64-neon-builtins-base.cc: public: + auto len = TYPE_VECTOR_SUBPARTS (vec_type).to_constant (); + auto mask_type = build_vector_type (sizetype, len); + -+ auto start = secondary_p ? len / 2 : 0; ++ auto start = (secondary_p ^ BYTES_BIG_ENDIAN) ? len / 2 : 0; + tree_vector_builder builder (mask_type, len, 1); + + for (auto i = 0U; i < len / 2; i++) 7: 43ff824fb32b = 7: a20919e47347 aarch64: Port NEON reinterpret intrinsics to pragma-based framework -- 2.54.0
