On 10/09/12 16:11, Tejas Belagod wrote:
Hi,
This patch tightens the predicate for the CMP pattern. It makes it restrictive
to accept reg or zero as prescribed by the architecture.
Regression-tested on aarch64-none-elf. OK for aarch64-branch?
Thanks,
Tejas Belagod
ARM.
PS: This patch applies over vldn-vstn.txt sent out earlier.
Changelog:
2012-09-10 Tejas Belagod<tejas.bela...@arm.com>
gcc/
* config/aarch64/aarch64-simd.md (aarch64_cm<cmp><mode>): Tighten
predicate for operand 2 of the compare pattern to accept register
or zero.
* config/aarch64/predicates.md (aarch64_simd_reg_or_zero): New.
Tejas
This patch duplicated the definition of aarch64_simd_reg_or_zero
introduced by the earlier vld234 patch. I've committed the attached fix
to aarch64-branch and aarch64-4.7-branch
Cheers
/Marcus
2012-09-26 Marcus Shawcroft <marcus.shawcr...@arm.com>
* config/aarch64/predicates.md (aarch64_simd_reg_or_zero): Remove
duplicate.Index: gcc/config/aarch64/predicates.md
===================================================================
--- gcc/config/aarch64/predicates.md (revision 191754)
+++ gcc/config/aarch64/predicates.md (working copy)
@@ -295,9 +295,3 @@
{
return aarch64_simd_imm_zero_p (op, mode);
})
-
-(define_predicate "aarch64_simd_reg_or_zero"
- (and (match_code "reg,subreg,const_int,const_vector")
- (ior (match_operand 0 "register_operand")
- (ior (match_test "op == const0_rtx")
- (match_test "aarch64_simd_imm_zero_p (op, mode)")))))
