This is my 2nd and possibly last patch for this work item.
This change takes loops of the form:
for (int <i> = 0; <i> < FIRST_PSEUDO_REGISTER; <i>++)
if (TEST_HARD_REG_BIT (<set>, <i>))
<body that doesn't change i or set>
and carries out the necessary refactoring to rewrite them as:
hard_reg_set_iterator hrsi; [...]
EXECUTE_IF_SET_IN_HARD_REG_SET (<set>, 0, <i>, hrsi)
<body that doesn't change i or set>
in loops where expressing <set> does not involve <i>.
gcc/
* config/m32c/m32c.cc (m32c_class_max_nregs): Improved 1 loop.
* config/m68k/m68k.cc (m68k_conditional_register_usage): Improved 1
loop.
(m68k_zero_call_used_regs): Improved 1 loop.
* config/pdp11/pdp11.cc (pdp11_conditional_register_usage): Improved 1
loop.
* ira-int.h (ira_hard_reg_set_intersection_p): Improved 1 loop.
* ira-lives.cc (process_bb_node_lives): Improved 1 loop.
* ira.cc (setup_class_hard_regs): Improved 1 loop.
(update_equiv_regs_prescan): Improved 1 loop.
(build_insn_chain): Improved 1 loop.
* lra_eliminations.cc (spill_pseudos): Improved 1 loop.
* optabs.cc (expand_asm_reg_clobber_mem_blockage): Improved 2 loops.
* postreload.cc (reload_combine): Improved 3 loops.
* reginfo.cc (init_reg_sets_1): Improved 1 loop.
* regrename.cc (init_rename_info): Improved 1 loop.
* reload1.cc (maybe_fix_stack_asms): Improved 1 loop.
(update_eliminables): Improved 1 loop.
* rtl-ssa/insns.cc (function_info::record_call_clobbers): Improved 1
loop.
* sched-deps.cc (sched_analyze_insn): Fix indentation.
* sel-sched-dump.cc (dump_insn_vector): Improved 1 loop.
Signed-off-by: Kevin Stefanov <[email protected]>
---
I have gone over each occurence under gcc/ returned by:
grep -r -C 5 "TEST_HARD_REG_BIT" | grep --color=always -E "for|$"
to get all hits for TEST_HARD_REG_BIT, with any occurences of "for"
in the surrounding context lines being highlighted in red, so I can
skip any occurences that are not part of a for-loop to begin with.
These are all the for loops I found that matched the pattern required
for this refactoring. I had sent a first small patch with a single
loop refactored a month ago on the file we talked about on bugzilla.
(sched-deps.cc) and I never received any feedback on that so, just a
light reminder for that too. I do not have write access yet so when
code review passes and we're good to go, I'd appreciate if someone could
do that part for me. Let me know if I have miscellaneous things like
indentation or changelog style to fix. One last thing, I forgot to
add a [1/X] numbering marker on my first commit from a month ago,
so what is the recommended way for me to fix that, given that this
commit here is technically [2/X] now?
Here is my output from comparing the test results of this change and
that of a pristine GCC build:
Tests that now work, but didn't before (6 tests):
g++: g++.dg/gomp/deprecate-1.C -std=c++20 expected multiline pattern lines
119-121
g++: g++.dg/gomp/deprecate-1.C -std=c++20 (test for excess errors)
g++: g++.dg/gomp/deprecate-1.C -std=c++26 expected multiline pattern lines
119-121
g++: g++.dg/gomp/deprecate-1.C -std=c++26 (test for excess errors)
g++: g++.dg/gomp/deprecate-1.C -std=c++98 expected multiline pattern lines
119-121
g++: g++.dg/gomp/deprecate-1.C -std=c++98 (test for excess errors)
New tests that PASS (1 tests):
g++: g++.dg/modules/compile-std1.C module-cmi <bits/stdc++.h>
(gcm.cache/home/hypervisor123/tmp/repos/gcc/objdir-contrib/x86_64-pc-linux-gnu/libstdc++-v3/include/x86_64-pc-linux-gnu/bits/stdc++.h.gcm)
Old tests that passed, that have disappeared (1 tests): (Eeek!)
g++: g++.dg/modules/compile-std1.C module-cmi <bits/stdc++.h>
(gcm.cache/home/hypervisor123/tmp/repos/gcc/objdir/x86_64-pc-linux-gnu/libstdc++-v3/include/x86_64-pc-linux-gnu/bits/stdc++.h.gcm)
## Differences found
# 1 differences in 16 common sum files found
gcc/config/m32c/m32c.cc | 15 +++++++------
gcc/config/m68k/m68k.cc | 10 ++++-----
gcc/config/pdp11/pdp11.cc | 4 ++--
gcc/ira-int.h | 10 ++++-----
gcc/ira-lives.cc | 9 ++++----
gcc/ira.cc | 24 +++++++++++++-------
gcc/lra-eliminations.cc | 8 ++++---
gcc/optabs.cc | 21 +++++++++--------
gcc/postreload.cc | 33 ++++++++++++++-------------
gcc/reginfo.cc | 14 ++++++------
gcc/regrename.cc | 20 ++++++++---------
gcc/reload1.cc | 47 ++++++++++++++++++++-------------------
gcc/rtl-ssa/insns.cc | 7 ++++--
gcc/sched-deps.cc | 25 +++++++++++----------
gcc/sel-sched-dump.cc | 12 +++++-----
15 files changed, 141 insertions(+), 118 deletions(-)
diff --git a/gcc/config/m32c/m32c.cc b/gcc/config/m32c/m32c.cc
index b18246df05e..b0709dcca57 100644
--- a/gcc/config/m32c/m32c.cc
+++ b/gcc/config/m32c/m32c.cc
@@ -793,13 +793,14 @@ m32c_class_max_nregs (reg_class_t regclass, machine_mode
mode)
int rn;
unsigned char max = 0;
- for (rn = 0; rn < FIRST_PSEUDO_REGISTER; rn++)
- if (TEST_HARD_REG_BIT (reg_class_contents[(int) regclass], rn))
- {
- unsigned char n = m32c_hard_regno_nregs (rn, mode);
- if (max < n)
- max = n;
- }
+ hard_reg_set_iterator hrsi;
+ EXECUTE_IF_SET_IN_HARD_REG_SET
+ (reg_class_contents[(int) regclass], 0, rn, hrsi)
+ {
+ unsigned char n = m32c_hard_regno_nregs (rn, mode);
+ if (max < n)
+ max = n;
+ }
return max;
}
diff --git a/gcc/config/m68k/m68k.cc b/gcc/config/m68k/m68k.cc
index 18fc2cacf43..8652ff56273 100644
--- a/gcc/config/m68k/m68k.cc
+++ b/gcc/config/m68k/m68k.cc
@@ -7118,9 +7118,9 @@ m68k_conditional_register_usage (void)
if (!TARGET_HARD_FLOAT)
{
x = reg_class_contents[FP_REGS];
- for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
- if (TEST_HARD_REG_BIT (x, i))
- fixed_regs[i] = call_used_regs[i] = 1;
+ hard_reg_set_iterator hrsi;
+ EXECUTE_IF_SET_IN_HARD_REG_SET (x, 0, i, hrsi)
+ fixed_regs[i] = call_used_regs[i] = 1;
}
if (flag_pic)
fixed_regs[PIC_REG] = call_used_regs[PIC_REG] = 1;
@@ -7211,8 +7211,8 @@ m68k_zero_call_used_regs (HARD_REG_SET
need_zeroed_hardregs)
{
rtx zero_fpreg = NULL_RTX;
- for (unsigned int regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
- if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno))
+ hard_reg_set_iterator hrsi;
+ EXECUTE_IF_SET_IN_HARD_REG_SET (need_zeroed_hardregs, 0, regno, hrsi)
{
rtx reg, zero;
diff --git a/gcc/config/pdp11/pdp11.cc b/gcc/config/pdp11/pdp11.cc
index 07800faecf8..77c5d2ccb01 100644
--- a/gcc/config/pdp11/pdp11.cc
+++ b/gcc/config/pdp11/pdp11.cc
@@ -2214,8 +2214,8 @@ pdp11_conditional_register_usage (void)
if (!TARGET_FPU)
{
x = reg_class_contents[FPU_REGS];
- for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ )
- if (TEST_HARD_REG_BIT (x, i))
+ hard_reg_set_iterator hrsi;
+ EXECUTE_IF_SET_IN_HARD_REG_SET (x, 0, i, hrsi)
fixed_regs[i] = call_used_regs[i] = 1;
}
diff --git a/gcc/ira-int.h b/gcc/ira-int.h
index 6726a0f4cad..3c0db7e6220 100644
--- a/gcc/ira-int.h
+++ b/gcc/ira-int.h
@@ -1441,11 +1441,11 @@ ira_hard_reg_set_intersection_p (int hard_regno,
machine_mode mode,
inline int
hard_reg_set_size (HARD_REG_SET set)
{
- int i, size;
-
- for (size = i = 0; i < FIRST_PSEUDO_REGISTER; i++)
- if (TEST_HARD_REG_BIT (set, i))
- size++;
+ int size = 0;
+ unsigned int i;
+ hard_reg_set_iterator hrsi;
+ EXECUTE_IF_SET_IN_HARD_REG_SET (set, 0, i, hrsi)
+ size++;
return size;
}
diff --git a/gcc/ira-lives.cc b/gcc/ira-lives.cc
index 04e586343c8..1caa175f5cb 100644
--- a/gcc/ira-lives.cc
+++ b/gcc/ira-lives.cc
@@ -1309,7 +1309,7 @@ static void
process_bb_node_lives (ira_loop_tree_node_t loop_tree_node)
{
int i, freq;
- unsigned int j;
+ unsigned int j, k;
basic_block bb;
rtx_insn *insn;
bitmap_iterator bi;
@@ -1330,12 +1330,13 @@ process_bb_node_lives (ira_loop_tree_node_t
loop_tree_node)
sparseset_clear (objects_live);
REG_SET_TO_HARD_REG_SET (hard_regs_live, reg_live_out);
hard_regs_live &= ~(eliminable_regset | ira_no_alloc_regs);
- for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
- if (TEST_HARD_REG_BIT (hard_regs_live, i))
+ hard_reg_set_iterator hrsi;
+ k = 0;
+ EXECUTE_IF_SET_IN_HARD_REG_SET (hard_regs_live, 0, k, hrsi)
{
enum reg_class aclass, pclass, cl;
- aclass = ira_allocno_class_translate[REGNO_REG_CLASS (i)];
+ aclass = ira_allocno_class_translate[REGNO_REG_CLASS (k)];
pclass = ira_pressure_class_translate[aclass];
for (j = 0;
(cl = ira_reg_class_super_classes[pclass][j])
diff --git a/gcc/ira.cc b/gcc/ira.cc
index d65e1b97ed8..8d08ad87474 100644
--- a/gcc/ira.cc
+++ b/gcc/ira.cc
@@ -466,6 +466,7 @@ static void
setup_class_hard_regs (void)
{
int cl, i, hard_regno, n;
+ unsigned int j;
HARD_REG_SET processed_hard_reg_set;
ira_assert (SHRT_MAX >= FIRST_PSEUDO_REGISTER);
@@ -497,9 +498,12 @@ setup_class_hard_regs (void)
}
}
ira_class_hard_regs_num[cl] = n;
- for (n = 0, i = 0; i < FIRST_PSEUDO_REGISTER; i++)
- if (TEST_HARD_REG_BIT (temp_hard_regset, i))
- ira_non_ordered_class_hard_regs[cl][n++] = i;
+ n = 0;
+ j = 0;
+ hard_reg_set_iterator hrsi;
+ EXECUTE_IF_SET_IN_HARD_REG_SET (temp_hard_regset, 0, j ,hrsi)
+ ira_non_ordered_class_hard_regs[cl][n++] = j;
+
ira_assert (ira_class_hard_regs_num[cl] == n);
}
}
@@ -3610,10 +3614,14 @@ update_equiv_regs_prescan (void)
}
HARD_REG_SET extra_caller_saves = callee_abis.caller_save_regs (*crtl->abi);
+
+ hard_reg_set_iterator hrsi;
+ unsigned int regno = 0;
if (!hard_reg_set_empty_p (extra_caller_saves))
- for (unsigned int regno = 0; regno < FIRST_PSEUDO_REGISTER; ++regno)
- if (TEST_HARD_REG_BIT (extra_caller_saves, regno))
+ {
+ EXECUTE_IF_SET_IN_HARD_REG_SET (extra_caller_saves, 0, regno, hrsi)
df_set_regs_ever_live (regno, true);
+ }
}
/* Find registers that are equivalent to a single value throughout the
@@ -4387,9 +4395,9 @@ build_insn_chain (void)
sbitmap *live_subregs = XCNEWVEC (sbitmap, max_regno);
auto_bitmap live_subregs_used;
- for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
- if (TEST_HARD_REG_BIT (eliminable_regset, i))
- bitmap_set_bit (elim_regset, i);
+ hard_reg_set_iterator hrsi;
+ EXECUTE_IF_SET_IN_HARD_REG_SET (eliminable_regset, 0, i, hrsi)
+ bitmap_set_bit (elim_regset, i);
FOR_EACH_BB_REVERSE_FN (bb, cfun)
{
bitmap_iterator bi;
diff --git a/gcc/lra-eliminations.cc b/gcc/lra-eliminations.cc
index 8e68cb70dcf..9276714687a 100644
--- a/gcc/lra-eliminations.cc
+++ b/gcc/lra-eliminations.cc
@@ -1132,6 +1132,7 @@ static int
spill_pseudos (HARD_REG_SET set, int *spilled_pseudos)
{
int i, n;
+ unsigned int j;
bitmap_head to_process;
rtx_insn *insn;
@@ -1140,9 +1141,10 @@ spill_pseudos (HARD_REG_SET set, int *spilled_pseudos)
if (lra_dump_file != NULL)
{
fprintf (lra_dump_file, " Spilling non-eliminable hard regs:");
- for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
- if (TEST_HARD_REG_BIT (set, i))
- fprintf (lra_dump_file, " %d", i);
+ j = 0;
+ hard_reg_set_iterator hrsi;
+ EXECUTE_IF_SET_IN_HARD_REG_SET (set, 0, j, hrsi)
+ fprintf (lra_dump_file, " %d", j);
fprintf (lra_dump_file, "\n");
}
bitmap_initialize (&to_process, ®_obstack);
diff --git a/gcc/optabs.cc b/gcc/optabs.cc
index e813cf9b215..2e1f1f9bc9c 100644
--- a/gcc/optabs.cc
+++ b/gcc/optabs.cc
@@ -7508,9 +7508,11 @@ expand_asm_reg_clobber_mem_blockage (HARD_REG_SET regs)
rtx asm_op, clob_mem;
unsigned int num_of_regs = 0;
- for (unsigned int i = 0; i < FIRST_PSEUDO_REGISTER; i++)
- if (TEST_HARD_REG_BIT (regs, i))
- num_of_regs++;
+ unsigned int i;
+ hard_reg_set_iterator hrsi1;
+ i = 0;
+ EXECUTE_IF_SET_IN_HARD_REG_SET (regs, 0, i, hrsi1)
+ num_of_regs++;
asm_op = gen_rtx_ASM_OPERANDS (VOIDmode, "", "", 0,
rtvec_alloc (0), rtvec_alloc (0),
@@ -7529,12 +7531,13 @@ expand_asm_reg_clobber_mem_blockage (HARD_REG_SET regs)
if (num_of_regs > 0)
{
unsigned int j = 2;
- for (unsigned int i = 0; i < FIRST_PSEUDO_REGISTER; i++)
- if (TEST_HARD_REG_BIT (regs, i))
- {
- RTVEC_ELT (v, j) = gen_rtx_CLOBBER (VOIDmode, regno_reg_rtx[i]);
- j++;
- }
+ hard_reg_set_iterator hrsi2;
+ i = 0;
+ EXECUTE_IF_SET_IN_HARD_REG_SET (regs, 0, i, hrsi2)
+ {
+ RTVEC_ELT (v, j) = gen_rtx_CLOBBER (VOIDmode, regno_reg_rtx[i]);
+ j++;
+ }
gcc_assert (j == (num_of_regs + 2));
}
diff --git a/gcc/postreload.cc b/gcc/postreload.cc
index 80a65796efb..9d798880ea6 100644
--- a/gcc/postreload.cc
+++ b/gcc/postreload.cc
@@ -1338,14 +1338,15 @@ reload_combine (void)
last_index_reg = -1;
else if (first_index_reg == -1 && last_index_reg == 0)
{
- for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
- if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
- {
- if (first_index_reg == -1)
- first_index_reg = r;
+ hard_reg_set_iterator hrsi1;
+ EXECUTE_IF_SET_IN_HARD_REG_SET
+ (reg_class_contents[INDEX_REG_CLASS], 0, r, hrsi1)
+ {
+ if (first_index_reg == -1)
+ first_index_reg = r;
- last_index_reg = r;
- }
+ last_index_reg = r;
+ }
/* If no index register is available, we can quit now. Set
LAST_INDEX_REG
to -1 so we'll know to quit early the next time we get here. */
@@ -1440,12 +1441,12 @@ reload_combine (void)
rtx link;
HARD_REG_SET used_regs = insn_callee_abi (insn).full_reg_clobbers ();
- for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
- if (TEST_HARD_REG_BIT (used_regs, r))
- {
- reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
- reg_state[r].store_ruid = reload_combine_ruid;
- }
+ hard_reg_set_iterator hrsi2;
+ EXECUTE_IF_SET_IN_HARD_REG_SET (used_regs, 0, r, hrsi2)
+ {
+ reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
+ reg_state[r].store_ruid = reload_combine_ruid;
+ }
for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
link = XEXP (link, 1))
@@ -1480,9 +1481,11 @@ reload_combine (void)
live = &ever_live_at_start;
if (live)
- for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
- if (TEST_HARD_REG_BIT (*live, r))
+ {
+ hard_reg_set_iterator hrsi3;
+ EXECUTE_IF_SET_IN_HARD_REG_SET (*live, 0, r, hrsi3)
reg_state[r].use_index = -1;
+ }
}
reload_combine_note_use (&PATTERN (insn), insn, reload_combine_ruid,
diff --git a/gcc/reginfo.cc b/gcc/reginfo.cc
index 9b515870d55..c06ab4dea72 100644
--- a/gcc/reginfo.cc
+++ b/gcc/reginfo.cc
@@ -269,13 +269,13 @@ init_reg_sets_1 (void)
for (i = 0; i < N_REG_CLASSES; i++)
{
bool any_nonfixed = false;
- for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
- if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
- {
- reg_class_size[i]++;
- if (!fixed_regs[j])
- any_nonfixed = true;
- }
+ hard_reg_set_iterator hrsi;
+ EXECUTE_IF_SET_IN_HARD_REG_SET (reg_class_contents[i], 0, j, hrsi)
+ {
+ reg_class_size[i]++;
+ if (!fixed_regs[j])
+ any_nonfixed = true;
+ }
class_only_fixed_regs[i] = !any_nonfixed;
}
diff --git a/gcc/regrename.cc b/gcc/regrename.cc
index b0021019c69..5b625cd27df 100644
--- a/gcc/regrename.cc
+++ b/gcc/regrename.cc
@@ -630,17 +630,17 @@ init_rename_info (class bb_rename_info *p, basic_block bb)
remove_range_from_hard_reg_set (&live_hard_regs, i, iri->nregs);
}
}
- for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+ struct incoming_reg_info *iri;
+ unsigned int j = 0;
+ hard_reg_set_iterator hrsi;
+ EXECUTE_IF_SET_IN_HARD_REG_SET (start_chains_set, 0, j, hrsi)
{
- struct incoming_reg_info *iri = p->incoming + i;
- if (TEST_HARD_REG_BIT (start_chains_set, i))
- {
- du_head_p chain;
- if (dump_file)
- fprintf (dump_file, "opening incoming chain\n");
- chain = create_new_chain (i, iri->nregs, NULL, NULL, NO_REGS);
- bitmap_set_bit (&p->incoming_open_chains_set, chain->id);
- }
+ du_head_p chain;
+ if (dump_file)
+ fprintf (dump_file, "opening incoming chain\n");
+ iri = p->incoming + j;
+ chain = create_new_chain (j, iri->nregs, NULL, NULL, NO_REGS);
+ bitmap_set_bit (&p->incoming_open_chains_set, chain->id);
}
}
diff --git a/gcc/reload1.cc b/gcc/reload1.cc
index 8cac4011c46..c4562a4eb3c 100644
--- a/gcc/reload1.cc
+++ b/gcc/reload1.cc
@@ -1403,12 +1403,13 @@ maybe_fix_stack_asms (void)
constraints, must be usable as reload registers. So clear them
out of the life information. */
allowed &= clobbered;
- for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
- if (TEST_HARD_REG_BIT (allowed, i))
- {
- CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
- CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
- }
+ hard_reg_set_iterator hrsi;
+ unsigned int j = 0;
+ EXECUTE_IF_SET_IN_HARD_REG_SET (allowed, 0, j, hrsi)
+ {
+ CLEAR_REGNO_REG_SET (&chain->live_throughout, j);
+ CLEAR_REGNO_REG_SET (&chain->dead_or_set, j);
+ }
}
#endif
@@ -3919,29 +3920,29 @@ update_eliminables (HARD_REG_SET *pset)
static bool
update_eliminables_and_spill (void)
{
- int i;
+ unsigned int i;
bool did_spill = false;
HARD_REG_SET to_spill;
CLEAR_HARD_REG_SET (to_spill);
update_eliminables (&to_spill);
used_spill_regs &= ~to_spill;
- for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
- if (TEST_HARD_REG_BIT (to_spill, i))
- {
- spill_hard_reg (i, 1);
- did_spill = true;
-
- /* Regardless of the state of spills, if we previously had
- a register that we thought we could eliminate, but now
- cannot eliminate, we must run another pass.
-
- Consider pseudos which have an entry in reg_equiv_* which
- reference an eliminable register. We must make another pass
- to update reg_equiv_* so that we do not substitute in the
- old value from when we thought the elimination could be
- performed. */
- }
+ hard_reg_set_iterator hrsi;
+ EXECUTE_IF_SET_IN_HARD_REG_SET (to_spill, 0, i, hrsi)
+ {
+ spill_hard_reg (i, 1);
+ did_spill = true;
+
+ /* Regardless of the state of spills, if we previously had
+ a register that we thought we could eliminate, but now
+ cannot eliminate, we must run another pass.
+
+ Consider pseudos which have an entry in reg_equiv_* which
+ reference an eliminable register. We must make another pass
+ to update reg_equiv_* so that we do not substitute in the
+ old value from when we thought the elimination could be
+ performed. */
+ }
return did_spill;
}
diff --git a/gcc/rtl-ssa/insns.cc b/gcc/rtl-ssa/insns.cc
index 317a5809b18..5097752e1ac 100644
--- a/gcc/rtl-ssa/insns.cc
+++ b/gcc/rtl-ssa/insns.cc
@@ -632,8 +632,10 @@ function_info::record_call_clobbers (build_info &bi,
insn_info *insn,
m_clobbered_by_calls |= abi.full_and_partial_reg_clobbers ();
}
else
- for (unsigned int regno = 0; regno < FIRST_PSEUDO_REGISTER; ++regno)
- if (TEST_HARD_REG_BIT (abi.full_reg_clobbers (), regno))
+ {
+ hard_reg_set_iterator hrsi;
+ unsigned int regno = 0;
+ EXECUTE_IF_SET_IN_HARD_REG_SET (abi.full_reg_clobbers (), 0, regno, hrsi)
{
def_info *def = m_defs[regno + 1];
if (!def || def->last_def ()->insn () != insn)
@@ -645,6 +647,7 @@ function_info::record_call_clobbers (build_info &bi,
insn_info *insn,
bi.record_reg_def (def);
}
}
+ }
}
// Called while building SSA form using BI. Record that INSN contains
diff --git a/gcc/sched-deps.cc b/gcc/sched-deps.cc
index ef4728d753b..c24c6ae99e4 100644
--- a/gcc/sched-deps.cc
+++ b/gcc/sched-deps.cc
@@ -3149,21 +3149,22 @@ sched_analyze_insn (class deps_desc *deps, rtx x,
rtx_insn *insn)
}
}
- hard_reg_set_iterator hrsi;
+ hard_reg_set_iterator hrsi;
EXECUTE_IF_SET_IN_HARD_REG_SET(implicit_reg_pending_uses, 0, i , hrsi)
- {
- struct deps_reg *reg_last = &deps->reg_last[i];
- add_dependence_list (insn, reg_last->sets, 0, REG_DEP_TRUE, false);
- add_dependence_list (insn, reg_last->implicit_sets, 0, REG_DEP_ANTI,
- false);
- add_dependence_list (insn, reg_last->clobbers, 0, REG_DEP_TRUE,
false);
-
- if (!deps->readonly)
{
- reg_last->uses = alloc_INSN_LIST (insn, reg_last->uses);
- reg_last->uses_length++;
+ struct deps_reg *reg_last = &deps->reg_last[i];
+ add_dependence_list (insn, reg_last->sets, 0, REG_DEP_TRUE, false);
+ add_dependence_list (insn, reg_last->implicit_sets, 0, REG_DEP_ANTI,
+ false);
+ add_dependence_list (insn, reg_last->clobbers, 0, REG_DEP_TRUE,
+ false);
+
+ if (!deps->readonly)
+ {
+ reg_last->uses = alloc_INSN_LIST (insn, reg_last->uses);
+ reg_last->uses_length++;
+ }
}
- }
if (targetm.sched.exposed_pipeline)
{
diff --git a/gcc/sel-sched-dump.cc b/gcc/sel-sched-dump.cc
index 146e819bc6b..e0f20801fa6 100644
--- a/gcc/sel-sched-dump.cc
+++ b/gcc/sel-sched-dump.cc
@@ -539,14 +539,14 @@ dump_insn_vector (rtx_vec_t succs)
static void
print_hard_reg_set (FILE *file, const char *prefix, HARD_REG_SET set)
{
- int i;
+ unsigned int i;
fprintf (file, "%s{ ", prefix);
- for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
- {
- if (TEST_HARD_REG_BIT (set, i))
- fprintf (file, "%d ", i);
- }
+
+ hard_reg_set_iterator hrsi;
+ EXECUTE_IF_SET_IN_HARD_REG_SET (set, 0, i, hrsi)
+ fprintf (file, "%d ", i);
+
fprintf (file, "}\n");
}
--
2.53.0
