On Mon, Mar 02, 2026 at 07:21:26AM -0500, Vijay Shankar wrote:
>
> Hello,
>
> Last patch failed to include v3 change list due to
> spacing issues under subject line.
> Please consider this patch instead
>
> Changes from v3:
> -Update test cases to use scan-assembler-not
> -Better wording
>
> Changes from v2:
> -Commit message has better wording.
> -Updated changelog wording.
>
> Changes from v1:
> -Formatted the patch.
> -Modified the builtin so that instructions are
> consistent. This was missed last time.
>
> Thank you,
> vijay
One meta comment that does not affect this bug. In looking at GCC, it
appears we do not generate xsrdpic for the scalar builtin 'nearbyint'.
We should open up a a bug for GCC 17 to possibly generate this
instruction, assuming we get the trap behavior correct (I don't know if
xsrdpic meets the conditions).
In terms of the vsx-vector-2.c test case, you use:
/* { dg-final { scan-assembler "xvrspi " } } */
I.e. having a space in the scan-assembler.
I tend to prefer not having spaces in scan-assebler. Instead we should
use {\m and \M} like the vsx-vector-6.c test case uses:
/* { dg-final { scan-assembler-not {\mxvrspi\M} } } */
> This patch emits instruction with proper rounding mode for
> vec_nearbyint.Previously, xvrdpi was emitted which uses nearest away
> rounding mode but nearbyint requires rounding mode to be current
> rounding mode.
You should put a space after vec_nearbyint.
With those changes made, the patch is ok to submit.
>
> Bootstrapped and regtested on powerpc64le-linux-gnu with no regressions.
>
> 2026-01-22 Vijay Shankar <[email protected]>
>
> gcc/ChangeLog:
> PR target/113353
> * config/rs6000/rs6000.cc (rs6000_builtin_vectorized_function):
> Emit xvrdpic/xvrspic.
> * config/rs6000/rs6000-overload.def (__builtin_vec_nearbyint) :
> Modified bif-id and overload-id.
>
> gcc/testsuite/ChangeLog:
> PR target/113353
> * gcc.target/powerpc/vsx-vector-1.c: Fix testcase.
> * gcc.target/powerpc/vsx-vector-2.c: Fix testcase.
> * gcc.target/powerpc/vsx-vector-6-func-1op.c: Fix testcase.
> ---
> gcc/config/rs6000/rs6000-overload.def | 4 ++--
> gcc/config/rs6000/rs6000.cc | 4 ++--
> gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c | 2 +-
> gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c | 2 +-
> gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op.c | 6 ++----
> 5 files changed, 8 insertions(+), 10 deletions(-)
>
> diff --git a/gcc/config/rs6000/rs6000-overload.def
> b/gcc/config/rs6000/rs6000-overload.def
> index 5238c81b2..ef7b59ed1 100644
> --- a/gcc/config/rs6000/rs6000-overload.def
> +++ b/gcc/config/rs6000/rs6000-overload.def
> @@ -2644,9 +2644,9 @@
>
> [VEC_NEARBYINT, vec_nearbyint, __builtin_vec_nearbyint]
> vf __builtin_vec_nearbyint (vf);
> - XVRSPI XVRSPI_NBI
> + XVRSPIC XVRSPIC_NBI
> vd __builtin_vec_nearbyint (vd);
> - XVRDPI XVRDPI_NBI
> + XVRDPIC XVRDPIC_NBI
>
> [VEC_NEG, vec_neg, __builtin_vec_neg]
> vsc __builtin_vec_neg (vsc);
> diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
> index a4f60ecb5..148c278bd 100644
> --- a/gcc/config/rs6000/rs6000.cc
> +++ b/gcc/config/rs6000/rs6000.cc
> @@ -5696,12 +5696,12 @@ rs6000_builtin_vectorized_function (unsigned int fn,
> tree type_out,
> && flag_unsafe_math_optimizations
> && out_mode == DFmode && out_n == 2
> && in_mode == DFmode && in_n == 2)
> - return rs6000_builtin_decls[RS6000_BIF_XVRDPI];
> + return rs6000_builtin_decls[RS6000_BIF_XVRDPIC];
> if (VECTOR_UNIT_VSX_P (V4SFmode)
> && flag_unsafe_math_optimizations
> && out_mode == SFmode && out_n == 4
> && in_mode == SFmode && in_n == 4)
> - return rs6000_builtin_decls[RS6000_BIF_XVRSPI];
> + return rs6000_builtin_decls[RS6000_BIF_XVRSPIC];
> break;
> CASE_CFN_RINT:
> if (VECTOR_UNIT_VSX_P (V2DFmode)
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c
> b/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c
> index 4d705e46d..3d633b7a8 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c
> @@ -14,7 +14,7 @@
> /* { dg-final { scan-assembler "xvrdpip" } } */
> /* { dg-final { scan-assembler "xvrdpiz" } } */
> /* { dg-final { scan-assembler "xvrdpic" } } */
> -/* { dg-final { scan-assembler "xvrdpi " } } */
> +/* { dg-final { scan-assembler-not "xvrdpi " } } */
>
> #ifndef SIZE
> #define SIZE 1024
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c
> b/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c
> index a0fe088bb..02c4456b6 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c
> @@ -14,7 +14,7 @@
> /* { dg-final { scan-assembler "xvrspip" } } */
> /* { dg-final { scan-assembler "xvrspiz" } } */
> /* { dg-final { scan-assembler "xvrspic" } } */
> -/* { dg-final { scan-assembler "xvrspi " } } */
> +/* { dg-final { scan-assembler-not "xvrspi " } } */
>
> #ifndef SIZE
> #define SIZE 1024
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op.c
> b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op.c
> index 6d2c64b24..6f629c471 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op.c
> @@ -10,13 +10,11 @@
> /* { dg-final { scan-assembler-times {\mxvabssp\M} 1 } } */
> /* { dg-final { scan-assembler-times {\mxvrspip\M} 1 } } */
> /* { dg-final { scan-assembler-times {\mxvrspim\M} 1 } } */
> -/* { dg-final { scan-assembler-times {\mxvrspi\M} 1 } } */
> -/* { dg-final { scan-assembler-times {\mxvrspic\M} 1 } } */
> +/* { dg-final { scan-assembler-times {\mxvrspic\M} 2 } } */
> /* { dg-final { scan-assembler-times {\mxvrspiz\M} 1 } } */
> /* { dg-final { scan-assembler-times {\mxvabsdp\M} 1 } } */
> /* { dg-final { scan-assembler-times {\mxvrdpip\M} 1 } } */
> /* { dg-final { scan-assembler-times {\mxvrdpim\M} 1 } } */
> -/* { dg-final { scan-assembler-times {\mxvrdpi\M} 1 } } */
> -/* { dg-final { scan-assembler-times {\mxvrdpic\M} 1 } } */
> +/* { dg-final { scan-assembler-times {\mxvrdpic\M} 2 } } */
> /* { dg-final { scan-assembler-times {\mxvrdpiz\M} 1 } } */
> /* { dg-final { scan-assembler-times {\mxvsqrtdp\M} 1 } } */
> --
> 2.47.3
>
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: [email protected]
