Always enable LRA on RX targets.
Some Machine Descriptions did not work properly with LRA,
so their definitions have been changed.
ChangeLog:
* gcc/config/rx/predicates.md (rx_double_src_operand): New.
(rx_double_dest_operand): New.
* gcc/config/rx/rx-protos.h (rx_split_double_move): New helper
prototype.
(rx_relax_double_operands): Likewise.
* gcc/config/rx/rx.cc (rx_gen_move_template): Fix operation size in
unsigned extend.
(rx_gen_move_template): Remove DImode and DFmode.
(rx_enable_lra): Remove.
(rx_modes_tieable_p): Remove.
(rx_get_subword): New. Double word move helper.
(rx_split_double_move): Likewise.
(rx_relax_double_operands): Likewise.
(TARGET_LRA_P): Remove.
(TARGET_MODES_TIEABLE_P): Remove.
* gcc/config/rx/rx.h (WORD_REGISTER_OPERATIONS): Remove.
* gcc/config/rx/rx.md (mov<register_modes:mode>):
Restructure special treatment.
(movdi): Limit the arguments to make register allocation easier.
(movdf): Likewise.
(movdi_internal): New.
(movdf_internal): New.
(adddi3): New. simplify implementation.
(subdi3): Likewise.
(addsi3_flags): adddi3 is not use. Remove it.
(adc_internal): Likewise.
(*adc_flags): Likewise.
(adddi3_internal): Likewise.
(subsi3_flags): subsi3 not use. Remove it.
(sbb_internal): Likewise.
(*sbb_flags): Likewise.
(subdi3): Likewise.
(define_insn "addsi3_pid"): New.
(rotlsi3): New. Make the LRA path unaware of CC changes.
(rotrsi3): Likewise.
(ashlsi3): Likewise.
(ashrsi3): Likewise.
(lshrsi3): Likewise.
(*shift_noclobber): Likewise.
(*rotlsi3): Remove clobber CC.
(*rotrsi3): Likewise.
* gcc/config/rx/rx.opt (mlra): Remove.
Signed-off-by: Yoshinori Sato <[email protected]>
---
gcc/config/rx/predicates.md | 14 ++
gcc/config/rx/rx-protos.h | 2 +
gcc/config/rx/rx.cc | 118 +++++++----
gcc/config/rx/rx.h | 1 -
gcc/config/rx/rx.md | 409 ++++++++++++++----------------------
gcc/config/rx/rx.opt | 6 -
6 files changed, 258 insertions(+), 292 deletions(-)
diff --git a/gcc/config/rx/predicates.md b/gcc/config/rx/predicates.md
index c51a21449e2..8ef09203a3b 100644
--- a/gcc/config/rx/predicates.md
+++ b/gcc/config/rx/predicates.md
@@ -307,3 +307,17 @@
(define_predicate "rshift_operator"
(match_code "ashiftrt,lshiftrt")
)
+
+;; DI and DF are expanded into multiple mov instructions,
+;; so they require stronger constraints than regular move.
+(define_predicate "rx_double_src_operand"
+ (ior (and (match_code "reg,subreg,const_int,const_double")
+ (match_operand 0 "general_operand"))
+ (and (match_code "mem")
+ (match_operand 0 "rx_restricted_mem_operand"))))
+
+(define_predicate "rx_double_dest_operand"
+ (ior (and (match_code "reg,subreg")
+ (match_operand 0 "general_operand"))
+ (and (match_code "mem")
+ (match_operand 0 "rx_restricted_mem_operand"))))
diff --git a/gcc/config/rx/rx-protos.h b/gcc/config/rx/rx-protos.h
index 0c6e7934ed9..2aeb76d87e3 100644
--- a/gcc/config/rx/rx-protos.h
+++ b/gcc/config/rx/rx-protos.h
@@ -70,6 +70,8 @@ extern void rx_copy_reg_dead_or_unused_notes (rtx reg, const
rtx_insn* src,
extern bool rx_fuse_in_memory_bitop (rtx* operands, rtx_insn* curr_insn,
rtx (*gen_insn)(rtx, rtx));
+extern void rx_split_double_move (rtx* operands, machine_mode mode);
+extern void rx_relax_double_operands (rtx* operands, machine_mode mode);
/* Result value of rx_find_set_of_reg. */
struct set_of_reg
diff --git a/gcc/config/rx/rx.cc b/gcc/config/rx/rx.cc
index c5638817d08..f5d020db86e 100644
--- a/gcc/config/rx/rx.cc
+++ b/gcc/config/rx/rx.cc
@@ -970,7 +970,8 @@ rx_gen_move_template (rtx * operands, bool is_movu)
rtx src = operands[1];
/* Decide which extension, if any, should be given to the move instruction.
*/
- switch (CONST_INT_P (src) ? GET_MODE (dest) : GET_MODE (src))
+ /* When zero-extending, always check the size of the source. */
+ switch ((is_movu || MEM_P(src)) ? GET_MODE (src) : GET_MODE(dest))
{
case E_QImode:
/* The .B extension is not valid when
@@ -984,10 +985,9 @@ rx_gen_move_template (rtx * operands, bool is_movu)
loading an immediate into a register. */
extension = ".W";
break;
- case E_DFmode:
- case E_DImode:
case E_SFmode:
case E_SImode:
+ gcc_assert(! is_movu);
extension = ".L";
break;
case E_VOIDmode:
@@ -1025,18 +1025,8 @@ rx_gen_move_template (rtx * operands, bool is_movu)
else
dst_template = "%0";
- if (GET_MODE (dest) == DImode || GET_MODE (dest) == DFmode)
- {
- gcc_assert (! is_movu);
-
- if (REG_P (src) && REG_P (dest) && (REGNO (dest) == REGNO (src) + 1))
- sprintf (out_template, "mov.L\t%%H1, %%H0 ! mov.L\t%%1, %%0");
- else
- sprintf (out_template, "mov.L\t%%1, %%0 ! mov.L\t%%H1, %%H0");
- }
- else
- sprintf (out_template, "%s%s\t%s, %s", is_movu ? "movu" : "mov",
- extension, src_template, dst_template);
+ sprintf (out_template, "%s%s\t%s, %s", is_movu ? "movu" : "mov",
+ extension, src_template, dst_template);
return out_template;
}
@@ -3495,12 +3485,6 @@ rx_ok_to_inline (tree caller, tree callee)
|| lookup_attribute ("gnu_inline", DECL_ATTRIBUTES (callee)) != NULL_TREE;
}
-static bool
-rx_enable_lra (void)
-{
- return TARGET_ENABLE_LRA;
-}
-
rx_atomic_sequence::rx_atomic_sequence (const_tree fun_decl)
{
if (is_fast_interrupt_func (fun_decl) || is_interrupt_func (fun_decl))
@@ -3622,17 +3606,6 @@ rx_hard_regno_mode_ok (unsigned int regno, machine_mode)
return REGNO_REG_CLASS (regno) == GR_REGS;
}
-/* Implement TARGET_MODES_TIEABLE_P. */
-
-static bool
-rx_modes_tieable_p (machine_mode mode1, machine_mode mode2)
-{
- return ((GET_MODE_CLASS (mode1) == MODE_FLOAT
- || GET_MODE_CLASS (mode1) == MODE_COMPLEX_FLOAT)
- == (GET_MODE_CLASS (mode2) == MODE_FLOAT
- || GET_MODE_CLASS (mode2) == MODE_COMPLEX_FLOAT));
-}
-
/* Implement TARGET_C_MODE_FOR_FLOATING_TYPE. Return SFmode or DFmode
for TI_{LONG_,}DOUBLE_TYPE which is for {long,} double type, go with
the default one for the others. */
@@ -3644,6 +3617,81 @@ rx_c_mode_for_floating_type (enum tree_index ti)
return TARGET_64BIT_DOUBLES ? DFmode : SFmode;
return default_mode_for_floating_type (ti);
}
+
+static rtx
+rx_get_subword (rtx op, machine_mode mode, int reg_offset)
+{
+ int mem_offset = reg_offset * 4;
+ if (TARGET_BIG_ENDIAN_DATA)
+ mem_offset = 4 - mem_offset;
+
+ if (MEM_P (op))
+ {
+ rtx addr = XEXP (op, 0);
+ rtx new_addr = plus_constant (Pmode, addr, mem_offset);
+ rtx new_mem = gen_rtx_MEM (SImode, new_addr);
+ MEM_COPY_ATTRIBUTES (new_mem, op);
+ return new_mem;
+ }
+
+ if (REG_P (op) && REGNO (op) < FIRST_PSEUDO_REGISTER)
+ return gen_rtx_REG (SImode, REGNO (op) + reg_offset);
+
+ return simplify_gen_subreg (SImode, op, mode, mem_offset);
+}
+
+void
+rx_split_double_move (rtx * operands, machine_mode mode)
+{
+ rtx dest = operands[0];
+ rtx src = operands[1];
+
+ rtx real_dest = (GET_CODE (dest) == SUBREG) ? SUBREG_REG (dest) : dest;
+ rtx real_src = (GET_CODE (src) == SUBREG) ? SUBREG_REG (src) : src;
+
+ rtx dest_low, dest_high, src_low, src_high;
+
+ src_low = rx_get_subword (MEM_P (real_src) ? real_src : src, mode, 0);
+ src_high = rx_get_subword (MEM_P (real_src) ? real_src : src, mode, 1);
+
+ dest_low = rx_get_subword (MEM_P (real_dest) ? real_dest : dest, mode, 0);
+ dest_high = rx_get_subword (MEM_P (real_dest) ? real_dest : dest, mode, 1);
+
+ if (REG_P (operands[0]) && reg_overlap_mentioned_p (dest_low, operands[1]))
+ {
+ emit_move_insn (dest_high, src_high);
+ emit_move_insn (dest_low, src_low);
+ }
+ else
+ {
+ emit_move_insn (dest_low, src_low);
+ emit_move_insn (dest_high, src_high);
+ }
+}
+
+void
+rx_relax_double_operands(rtx * operands, machine_mode mode)
+{
+ if (MEM_P (operands[0]) && !rx_restricted_mem_operand (operands[0], mode))
+ {
+ rtx addr = XEXP (operands[0], 0);
+ addr = force_reg (Pmode, addr);
+ operands[0] = replace_equiv_address (operands[0], addr);
+ }
+
+ if (MEM_P (operands[1]) && !rx_restricted_mem_operand (operands[1], mode))
+ {
+ rtx addr = XEXP (operands[1], 0);
+ addr = force_reg (Pmode, addr);
+ operands[1] = replace_equiv_address (operands[1], addr);
+ }
+
+ if (MEM_P (operands[0]) && !REG_P (operands[1]))
+ {
+ operands[1] = force_reg (mode, operands[1]);
+ }
+}
+
#undef TARGET_NARROW_VOLATILE_BITFIELD
#define TARGET_NARROW_VOLATILE_BITFIELD
rx_narrow_volatile_bitfield
@@ -3786,17 +3834,11 @@ rx_c_mode_for_floating_type (enum tree_index ti)
#undef TARGET_WARN_FUNC_RETURN
#define TARGET_WARN_FUNC_RETURN rx_warn_func_return
-#undef TARGET_LRA_P
-#define TARGET_LRA_P rx_enable_lra
-
#undef TARGET_HARD_REGNO_NREGS
#define TARGET_HARD_REGNO_NREGS rx_hard_regno_nregs
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK rx_hard_regno_mode_ok
-#undef TARGET_MODES_TIEABLE_P
-#define TARGET_MODES_TIEABLE_P rx_modes_tieable_p
-
#undef TARGET_RTX_COSTS
#define TARGET_RTX_COSTS rx_rtx_costs
diff --git a/gcc/config/rx/rx.h b/gcc/config/rx/rx.h
index 8c95ad9477f..9a655d0b60d 100644
--- a/gcc/config/rx/rx.h
+++ b/gcc/config/rx/rx.h
@@ -160,7 +160,6 @@
#define POINTERS_EXTEND_UNSIGNED 1
#define FUNCTION_MODE QImode
#define CASE_VECTOR_MODE Pmode
-#define WORD_REGISTER_OPERATIONS 1
#define HAS_LONG_COND_BRANCH 0
#define HAS_LONG_UNCOND_BRANCH 0
diff --git a/gcc/config/rx/rx.md b/gcc/config/rx/rx.md
index a3d966efdcc..9d5a2bf4db7 100644
--- a/gcc/config/rx/rx.md
+++ b/gcc/config/rx/rx.md
@@ -574,18 +574,10 @@
(match_operand:register_modes 1 "general_operand"))]
""
{
- if (MEM_P (operands[0]) && MEM_P (operands[1]))
- operands[1] = copy_to_mode_reg (<register_modes:MODE>mode, operands[1]);
operands[0] = rx_maybe_pidify_operand (operands[0], 0);
operands[1] = rx_maybe_pidify_operand (operands[1], 0);
- if (GET_CODE (operands[0]) != REG
- && GET_CODE (operands[1]) == PLUS)
- operands[1] = copy_to_mode_reg (<register_modes:MODE>mode, operands[1]);
- if (GET_CODE (operands[1]) == PLUS && GET_MODE (operands[1]) == SImode)
- {
- emit_insn (gen_addsi3 (operands[0], XEXP (operands[1], 0), XEXP
(operands[1], 1)));
- DONE;
- }
+ if (MEM_P (operands[0]) && GET_CODE (operands[1]) == PLUS)
+ operands[1] = force_reg (<register_modes:MODE>mode, operands[1]);
if (CONST_INT_P (operand1)
&& ! rx_is_legitimate_constant (<register_modes:MODE>mode, operand1))
FAIL;
@@ -603,6 +595,68 @@
(set_attr "timings" "11,11,11,11,11,12,11,11,11,11,11,11")]
)
+(define_expand "movdi"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "")
+ (match_operand:DI 1 "general_operand" ""))]
+ ""
+ {
+ rx_relax_double_operands(operands, DImode);
+
+ emit_insn (gen_movdi_internal (operands[0], operands[1]));
+ DONE;
+ }
+)
+
+(define_insn "movdi_internal"
+ [(set (match_operand:DI 0 "rx_double_dest_operand" "=r,r,m")
+ (match_operand:DI 1 "rx_double_src_operand" "ri,m,r"))]
+ ""
+ "#"
+ [(set_attr "length" "8")]
+)
+
+(define_split
+ [(set (match_operand:DI 0 "nonimmediate_operand" "")
+ (match_operand:DI 1 "general_operand" ""))]
+ "reload_completed"
+ [(const_int 0)]
+ {
+ rx_split_double_move (operands, DImode);
+ DONE;
+ }
+)
+
+(define_expand "movdf"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "")
+ (match_operand:DF 1 "general_operand" ""))]
+ ""
+ {
+ rx_relax_double_operands(operands, DFmode);
+
+ emit_insn (gen_movdf_internal (operands[0], operands[1]));
+ DONE;
+ }
+)
+
+(define_insn "movdf_internal"
+ [(set (match_operand:DF 0 "rx_double_dest_operand" "=r,r,m")
+ (match_operand:DF 1 "rx_double_src_operand" "rF,m,r"))]
+ ""
+ "#"
+ [(set_attr "length" "8")]
+)
+
+(define_split
+ [(set (match_operand:DF 0 "nonimmediate_operand" "")
+ (match_operand:DF 1 "general_operand" ""))]
+ "reload_completed"
+ [(const_int 0)]
+ {
+ rx_split_double_move (operands, DFmode);
+ DONE;
+ }
+)
+
(define_insn "extend<small_int_modes:mode>si2"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(sign_extend:SI (match_operand:small_int_modes
@@ -928,50 +982,27 @@
(set_attr "length" "2,2,2,3,4,5,6,2,3,3,4,5,6,5")]
)
-;; A helper to expand the above with the CC_MODE filled in.
-(define_expand "addsi3_flags"
- [(parallel [(set (reg:CC_ZSC CC_REG)
- (compare:CC_ZSC
- (plus:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "rx_source_operand"))
- (const_int 0)))
- (set (match_operand:SI 0 "register_operand")
- (plus:SI (match_dup 1) (match_dup 2)))])]
-)
-
-(define_insn "adc_internal"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
- (plus:SI
- (plus:SI
- (ltu:SI (reg:CC CC_REG) (const_int 0))
- (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0"))
- (match_operand:SI 2 "rx_source_operand"
"r,Sint08,Sint16,Sint24,i,Q")))
- (clobber (reg:CC CC_REG))]
- "reload_completed"
- "adc\t%2, %0"
- [(set_attr "timings" "11,11,11,11,11,33")
- (set_attr "length" "3,4,5,6,7,6")]
+(define_insn "addsi3_pid"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (plus:SI (match_operand:SI 1 "register_operand" "%0")
+ (const:SI (unspec:SI [(match_operand:SI 2 "immediate_operand"
"i")] UNSPEC_PID_ADDR))))]
+ ""
+ "add\t%2, %0"
+ [(set_attr "length" "6")
+ (set_attr "timings" "11")]
)
-(define_insn "*adc_flags"
- [(set (reg CC_REG)
- (compare
- (plus:SI
- (plus:SI
- (ltu:SI (reg:CC CC_REG) (const_int 0))
- (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0"))
- (match_operand:SI 2 "rx_source_operand"
"r,Sint08,Sint16,Sint24,i,Q"))
- (const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
- (plus:SI
- (plus:SI
- (ltu:SI (reg:CC CC_REG) (const_int 0))
- (match_dup 1))
- (match_dup 2)))]
- "reload_completed && rx_match_ccmode (insn, CC_ZSCmode)"
- "adc\t%2, %0"
- [(set_attr "timings" "11,11,11,11,11,33")
- (set_attr "length" "3,4,5,6,7,6")]
+(define_insn "adddi3"
+ [(set (match_operand:DI 0 "register_operand" "=r,r,r")
+ (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0")
+ (match_operand:DI 2 "rx_source_operand" "r,i,Q")))
+ (clobber (reg:CC CC_REG))]
+ ""
+ {
+ return "add\t%L2, %L0\n\tadc\t%H2, %H0";
+ }
+ [(set_attr "length" "6")
+ (set_attr "timings" "22")]
)
;; Peepholes to match:
@@ -1007,93 +1038,6 @@
(plus:SI (match_dup 1) (const_int 0)))])]
)
-(define_expand "adddi3"
- [(set (match_operand:DI 0 "register_operand")
- (plus:DI (match_operand:DI 1 "register_operand")
- (match_operand:DI 2 "rx_source_operand")))]
- ""
-{
- rtx op0l, op0h, op1l, op1h, op2l, op2h;
-
- op0l = gen_lowpart (SImode, operands[0]);
- op1l = gen_lowpart (SImode, operands[1]);
- op2l = gen_lowpart (SImode, operands[2]);
- op0h = gen_highpart (SImode, operands[0]);
- op1h = gen_highpart (SImode, operands[1]);
- op2h = gen_highpart_mode (SImode, DImode, operands[2]);
-
- emit_insn (gen_adddi3_internal (op0l, op0h, op1l, op2l, op1h, op2h));
- DONE;
-})
-
-(define_insn_and_split "adddi3_internal"
- [(set (match_operand:SI 0 "register_operand" "=&r")
- (plus:SI (match_operand:SI 2 "register_operand" "r")
- (match_operand:SI 3 "rx_source_operand" "riQ")))
- (set (match_operand:SI 1 "register_operand" "=r")
- (plus:SI
- (plus:SI
- (ltu:SI (plus:SI (match_dup 2) (match_dup 3)) (match_dup 2))
- (match_operand:SI 4 "register_operand" "%1"))
- (match_operand:SI 5 "rx_source_operand" "riQ")))
- (clobber (match_scratch:SI 6 "=&r"))
- (clobber (reg:CC CC_REG))]
- ""
- "#"
- "reload_completed"
- [(const_int 0)]
-{
- rtx op0l = operands[0];
- rtx op0h = operands[1];
- rtx op1l = operands[2];
- rtx op2l = operands[3];
- rtx op1h = operands[4];
- rtx op2h = operands[5];
- rtx scratch = operands[6];
- rtx x;
-
- if (reg_overlap_mentioned_p (op0l, op1h))
- {
- emit_move_insn (scratch, op0l);
- op1h = scratch;
- if (reg_overlap_mentioned_p (op0l, op2h))
- op2h = scratch;
- }
- else if (reg_overlap_mentioned_p (op0l, op2h))
- {
- emit_move_insn (scratch, op0l);
- op2h = scratch;
- }
-
- if (rtx_equal_p (op0l, op1l))
- ;
- /* It is preferable that op0l == op1l... */
- else if (rtx_equal_p (op0l, op2l))
- x = op1l, op1l = op2l, op2l = x;
- /* ... but it is only a requirement if op2l == MEM. */
- else if (MEM_P (op2l))
- {
- /* Let's hope that we still have a scratch register free. */
- gcc_assert (op1h != scratch);
- emit_move_insn (scratch, op2l);
- op2l = scratch;
- }
-
- emit_insn (gen_addsi3_flags (op0l, op1l, op2l));
-
- if (rtx_equal_p (op0h, op1h))
- ;
- else if (rtx_equal_p (op0h, op2h))
- x = op1h, op1h = op2h, op2h = x;
- else
- {
- emit_move_insn (op0h, op1h);
- op1h = op0h;
- }
- emit_insn (gen_adc_internal (op0h, op1h, op2h));
- DONE;
-})
-
(define_insn_and_split "andsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
(and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0")
@@ -1455,11 +1399,20 @@
(set_attr "length" "2,2,3,4,5,6,2,3,5")]
)
-(define_insn "rotlsi3"
+(define_expand "rotlsi3"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (rotate:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "rx_shift_operand" "")))
+ (clobber (reg:CC CC_REG))]
+ ""
+ {
+ }
+)
+
+(define_insn "*rotlsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(rotate:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:SI 2 "rx_shift_operand" "rn")))
- (clobber (reg:CC CC_REG))]
+ (match_operand:SI 2 "rx_shift_operand" "rn")))]
""
"rotl\t%2, %0"
[(set_attr "length" "3")]
@@ -1477,11 +1430,20 @@
[(set_attr "length" "3")]
)
-(define_insn "rotrsi3"
+(define_expand "rotrsi3"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (rotatert:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "rx_shift_operand" "")))
+ (clobber (reg:CC CC_REG))]
+ ""
+ {
+ }
+)
+
+(define_insn "*rotrsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(rotatert:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:SI 2 "rx_shift_operand" "rn")))
- (clobber (reg:CC CC_REG))]
+ (match_operand:SI 2 "rx_shift_operand" "rn")))]
""
"rotr\t%2, %0"
[(set_attr "length" "3")]
@@ -1499,7 +1461,16 @@
[(set_attr "length" "3")]
)
-(define_insn "ashrsi3"
+(define_expand "ashrsi3"
+ [(parallel [(set (match_operand:SI 0 "register_operand" "")
+ (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "rx_shift_operand" "")))
+ (clobber (reg:CC CC_REG))])]
+ ""
+ ""
+)
+
+(define_insn "*ashrsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
(ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
(match_operand:SI 2 "rx_shift_operand" "r,n,n")))
@@ -1527,7 +1498,16 @@
[(set_attr "length" "3,2,3")]
)
-(define_insn "lshrsi3"
+(define_expand "lshrsi3"
+ [(parallel [(set (match_operand:SI 0 "register_operand" "")
+ (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "rx_shift_operand" "")))
+ (clobber (reg:CC CC_REG))])]
+ ""
+ ""
+)
+
+(define_insn "*lshrsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
(match_operand:SI 2 "rx_shift_operand" "r,n,n")))
@@ -1555,7 +1535,16 @@
[(set_attr "length" "3,2,3")]
)
-(define_insn "ashlsi3"
+(define_expand "ashlsi3"
+ [(parallel [(set (match_operand:SI 0 "register_operand" "")
+ (ashift:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "rx_shift_operand" "")))
+ (clobber (reg:CC CC_REG))])]
+ ""
+ ""
+)
+
+(define_insn "*ashlsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
(ashift:SI (match_operand:SI 1 "register_operand" "0,0,r")
(match_operand:SI 2 "rx_shift_operand" "r,n,n")))
@@ -1583,6 +1572,20 @@
[(set_attr "length" "3,2,3")]
)
+;; This hides flag changes caused by shift instructions.
+(define_insn_and_split "*shift_noclobber"
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r")
+ (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r")
+ (match_operand:SI 2 "rx_shift_operand" "r,n,n")))]
+ ""
+ "#"
+ "reload_completed"
+ [(parallel [(set (match_dup 0)
+ (ashift:SI (match_dup 1) (match_dup 2)))
+ (clobber (reg:CC CC_REG))])]
+ ""
+)
+
;; Saturate to 32-bits
(define_insn_and_split "ssaddsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
@@ -1650,89 +1653,18 @@
(set_attr "length" "2,2,6,3,5")]
)
-;; A helper to expand the above with the CC_MODE filled in.
-(define_expand "subsi3_flags"
- [(parallel [(set (reg:CC_ZSC CC_REG)
- (compare:CC_ZSC
- (minus:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "rx_source_operand"))
- (const_int 0)))
- (set (match_operand:SI 0 "register_operand")
- (minus:SI (match_dup 1) (match_dup 2)))])]
-)
-
-(define_insn "sbb_internal"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (minus:SI
- (minus:SI
- (match_operand:SI 1 "register_operand" " 0,0")
- (match_operand:SI 2 "rx_compare_operand" " r,Q"))
- (geu:SI (reg:CC CC_REG) (const_int 0))))
- (clobber (reg:CC CC_REG))]
- "reload_completed"
- "sbb\t%2, %0"
- [(set_attr "timings" "11,33")
- (set_attr "length" "3,6")]
-)
-
-(define_insn "*sbb_flags"
- [(set (reg CC_REG)
- (compare
- (minus:SI
- (minus:SI
- (match_operand:SI 1 "register_operand" " 0,0")
- (match_operand:SI 2 "rx_compare_operand" " r,Q"))
- (geu:SI (reg:CC CC_REG) (const_int 0)))
- (const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=r,r")
- (minus:SI
- (minus:SI (match_dup 1) (match_dup 2))
- (geu:SI (reg:CC CC_REG) (const_int 0))))]
- "reload_completed"
- "sbb\t%2, %0"
- [(set_attr "timings" "11,33")
- (set_attr "length" "3,6")]
-)
-
-(define_expand "subdi3"
- [(set (match_operand:DI 0 "register_operand")
- (minus:DI (match_operand:DI 1 "register_operand")
- (match_operand:DI 2 "register_operand")))]
- ""
-{
- rtx op0l, op0h, op1l, op1h, op2l, op2h;
-
- op0l = gen_lowpart (SImode, operands[0]);
- op1l = gen_lowpart (SImode, operands[1]);
- op2l = gen_lowpart (SImode, operands[2]);
- op0h = gen_highpart (SImode, operands[0]);
- op1h = gen_highpart (SImode, operands[1]);
- op2h = gen_highpart_mode (SImode, DImode, operands[2]);
-
- emit_insn (gen_subdi3_internal (op0l, op0h, op1l, op2l, op1h, op2h));
- DONE;
-})
-
-(define_insn_and_split "subdi3_internal"
- [(set (match_operand:SI 0 "register_operand" "=&r,&r")
- (minus:SI (match_operand:SI 2 "register_operand" " 0, r")
- (match_operand:SI 3 "rx_compare_operand" "rQ, r")))
- (set (match_operand:SI 1 "register_operand" "= r, r")
- (minus:SI
- (minus:SI
- (match_operand:SI 4 "register_operand" " 1, 1")
- (match_operand:SI 5 "rx_compare_operand" " rQ,rQ"))
- (gtu:SI (match_dup 3) (match_dup 2))))
+(define_insn "subdi3"
+ [(set (match_operand:DI 0 "register_operand" "=r,r")
+ (minus:DI (match_operand:DI 1 "register_operand" "0,0")
+ (match_operand:DI 2 "rx_source_operand" "r,Q")))
(clobber (reg:CC CC_REG))]
""
- "#"
- "reload_completed"
- [(const_int 0)]
-{
- emit_insn (gen_subsi3_flags (operands[0], operands[2], operands[3]));
- emit_insn (gen_sbb_internal (operands[1], operands[4], operands[5]));
- DONE;
-})
+ {
+ return "sub\t%L2, %L0\n\tsbb\t%H2, %H0";
+ }
+ [(set_attr "length" "6")
+ (set_attr "timings" "22")]
+)
(define_insn_and_split "xorsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
@@ -1936,6 +1868,7 @@
[(set_attr "timings" "33")
(set_attr "length" "5")] ;; This length is corrected in
rx_adjust_insn_length
)
+
;; Floating Point Instructions
@@ -2869,21 +2802,3 @@
""
""
)
-
-(define_insn "movdi"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
- (match_operand:DI 1 "general_operand" "rmi"))]
- "TARGET_ENABLE_LRA"
- { return rx_gen_move_template (operands, false); }
- [(set_attr "length" "16")
- (set_attr "timings" "22")]
-)
-
-(define_insn "movdf"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=rm")
- (match_operand:DF 1 "general_operand" "rmi"))]
- "TARGET_ENABLE_LRA"
- { return rx_gen_move_template (operands, false); }
- [(set_attr "length" "16")
- (set_attr "timings" "22")]
-)
diff --git a/gcc/config/rx/rx.opt b/gcc/config/rx/rx.opt
index b3698f14594..779bc56b808 100644
--- a/gcc/config/rx/rx.opt
+++ b/gcc/config/rx/rx.opt
@@ -128,12 +128,6 @@ Enable the use the standard RX ABI where all stacked
function arguments are natu
;---------------------------------------------------
-mlra
-Target Mask(ENABLE_LRA)
-Enable the use of the LRA register allocator.
-
-;---------------------------------------------------
-
mallow-string-insns
Target Var(rx_allow_string_insns) Init(1)
Enables or disables the use of the SMOVF, SMOVB, SMOVU, SUNTIL, SWHILE and
RMPA instructions. Enabled by default.
--
2.47.3
