Here is a patch to add a new mips*-mti-elf target to GCC. This is similar
to the mips*-mti-linux-gnu target but for bare metal instead of linux.
The main difference between this new target and the existing mips*-sde-elf
target is that this version does not get built for as many different mips
architectures making the overall GCC build and test process faster and the
resulting cross compiler smaller because there are fewer different runtime
libraries.
I have attached 4 seperate patches because I made changes at the top level,
the top level config directory, the gcc directory, and the gcc test directory.
The top-level change is to not build the gprof directory for mips-mti-elf,
copying what we already do for mips-sde-elf. The config directory change
is to use -mcode-readable=pcrel instead of -mcode-xonly during compilation.
The flags do the same thing but -mcode-readable=pcrel is the prefered flag
to use and for my new target I have it set up to only understand the new
flag instead of both the old and new flags. The existing mips-sde-elf target
recognizes both old and new flags so it should not be affected by this
change. Most of the changes are two new files in the gcc directory for the
new target, and then there is one test that is skipped on mips-sde-elf and I
now skip it for mips-mti-elf too.
For this patch to work I also need a binutils patch which I will submit later
today, it adds the mips*-mti-elf target to binutils as a target that behaves
identically to mips*-sde-elf.
I tested each variation that the new target supports using newlib and the
gnu simulator. OK to checkin?
Top-level:
2012-09-12 Steve Ellcey <sell...@mips.com>
* configure.ac: Add mips*-mti-elf* target.
* configure: Regenerate.
diff --git a/configure.ac b/configure.ac
index a6f5828..3ddefdb 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1032,7 +1032,7 @@ case "${target}" in
microblaze*)
noconfigdirs="$noconfigdirs gprof"
;;
- mips*-sde-elf*)
+ mips*-sde-elf* | mips*-mti-elf*)
if test x$with_newlib = xyes; then
noconfigdirs="$noconfigdirs gprof"
fi
@@ -2251,7 +2251,7 @@ case "${target}" in
spu-*-*)
target_makefile_frag="config/mt-spu"
;;
- mips*-sde-elf*)
+ mips*-sde-elf* | mips*-mti-elf*)
target_makefile_frag="config/mt-sde"
;;
mipsisa*-*-elfoabi*)
===================================================================
2012-09-13 Steve Ellcey <sell...@mips.com>
* mt-sde: Change -mcode-xonly to -mcode-readable=pcrel.
diff --git a/config/mt-sde b/config/mt-sde
index d6992e4..a3fc1e1 100644
--- a/config/mt-sde
+++ b/config/mt-sde
@@ -1,10 +1,10 @@
# We default to building libraries optimised for size. We use
# -minterlink-mips16 so that the non-MIPS16 libraries can still be
-# linked against partly-MIPS16 code. The -mcode-xonly option allows
+# linked against partly-MIPS16 code. The -mcode-readable=pcrel option allows
# MIPS16 libraries to run on Harvard-style split I/D memories, so long
# as they have the D-to-I redirect for PC-relative loads. -mno-gpopt
# has two purposes: it allows libraries to be used in situations where
# $gp != our _gp, and it allows them to be built with -G8 while
# retaining link compatibility with -G0 and -G4.
-CFLAGS_FOR_TARGET += -Os -minterlink-mips16 -mcode-xonly -mno-gpopt
-CXXFLAGS_FOR_TARGET += -Os -minterlink-mips16 -mcode-xonly -mno-gpopt
+CFLAGS_FOR_TARGET += -Os -minterlink-mips16 -mcode-readable=pcrel -mno-gpopt
+CXXFLAGS_FOR_TARGET += -Os -minterlink-mips16 -mcode-readable=pcrel -mno-gpopt
===================================================================
2012-09-13 Steve Ellcey <sell...@mips.com>
* config.gcc (mips*-mti-elf*): New target.
* config/mips/mti-elf.h: New file.
* config/mips/t-mti-elf: New file.
diff --git a/gcc/config.gcc b/gcc/config.gcc
index ba366b3..9f5e170 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -1741,6 +1741,11 @@ mips*-*-linux*) # Linux MIPS,
either endian.
esac
test x$with_llsc != x || with_llsc=yes
;;
+mips*-mti-elf*)
+ tm_file="elfos.h newlib-stdint.h ${tm_file} mips/elf.h mips/sde.h
mips/mti-elf.h"
+ tmake_file="mips/t-mti-elf"
+ tm_defines="${tm_defines} MIPS_ISA_DEFAULT=33 MIPS_ABI_DEFAULT=ABI_32"
+ ;;
mips*-sde-elf*)
tm_file="elfos.h newlib-stdint.h ${tm_file} mips/elf.h mips/sde.h"
tmake_file="mips/t-sde"
diff --git a/gcc/config/mips/mti-elf.h b/gcc/config/mips/mti-elf.h
new file mode 100644
index 0000000..229555e
--- /dev/null
+++ b/gcc/config/mips/mti-elf.h
@@ -0,0 +1,56 @@
+/* Target macros for mips*-mti-elf targets.
+ Copyright (C) 2012
+ Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+
+#undef SYSROOT_SUFFIX_SPEC
+#define SYSROOT_SUFFIX_SPEC \
+
"%{mips32:/mips32}%{mips64:/mips64}%{mips64r2:/mips64r2}%{mips16:/mips16}%{msoft-float:/sof}%{mel|EL:/el}%{mabi=64:/64}%{mabi=n32:/n32}"
+
+/* This is idential to sde.h except for the ABI setting which defaults
+ to 32 instead of n32 on 32 bit architectures and the addition of
+ MIPS_ISA_SYNCI_SPEC. */
+
+#undef DRIVER_SELF_SPECS
+#define DRIVER_SELF_SPECS \
+ /* Make sure a -mips option is present. This helps us to pick \
+ the right multilib, and also makes the later specs easier \
+ to write. */ \
+ MIPS_ISA_LEVEL_SPEC, \
+ \
+ /* Infer the default float setting from -march. */ \
+ MIPS_ARCH_FLOAT_SPEC,
\
+ \
+ /* Infer the -msynci setting from -march if not explicitly set. */ \
+ MIPS_ISA_SYNCI_SPEC, \
+ \
+ /* If no ABI option is specified, infer one from the ISA level \
+ or -mgp setting. */ \
+ "%{!mabi=*:-mabi=32}", \
+ \
+ /* Remove a redundant -mfp64 for -mabi=n32; we want the !mfp64 \
+ multilibs. There's no need to check whether the architecture \
+ is 64-bit; cc1 will complain if it isn't. */ \
+ "%{mabi=n32: %<mfp64}", \
+ \
+ /* Make sure that an endian option is always present. This makes \
+ things like LINK_SPEC easier to write. */
\
+ "%{!EB:%{!EL:%(endian_spec)}}", \
+ \
+ /* Configuration-independent MIPS rules. */ \
+ BASE_DRIVER_SELF_SPECS
diff --git a/gcc/config/mips/t-mti-elf b/gcc/config/mips/t-mti-elf
new file mode 100644
index 0000000..5bc00a9
--- /dev/null
+++ b/gcc/config/mips/t-mti-elf
@@ -0,0 +1,21 @@
+# Copyright (C) 2007, 2008, 2011 Free Software Foundation, Inc.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GCC is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3. If not see
+# <http://www.gnu.org/licenses/>.
+
+MULTILIB_OPTIONS = EL msoft-float mips32/mips64/mips64r2
+MULTILIB_DIRNAMES = el sof mips32 mips64 mips64r2
+MULTILIB_MATCHES = EL=mel EB=meb
===================================================================
2012-09-13 Steve Ellcey <sell...@mips.com>
* gcc.target/mips/pr37362.c: Add mips*-mti-elf exception.
diff --git a/gcc/testsuite/gcc.target/mips/pr37362.c
b/gcc/testsuite/gcc.target/mips/pr37362.c
index a378366..da34b9d 100644
--- a/gcc/testsuite/gcc.target/mips/pr37362.c
+++ b/gcc/testsuite/gcc.target/mips/pr37362.c
@@ -1,5 +1,5 @@
/* mips*-sde-elf doesn't have 128-bit long doubles. */
-/* { dg-do compile { target { ! mips*-sde-elf } } } */
+/* { dg-do compile { target { ! mips*-sde-elf mips*-mti-elf } } } */
/* { dg-options "-march=mips64r2 -mabi=n32" } */
typedef float TFtype __attribute__((mode(TF)));
