On Thu, Jan 22, 2026 at 05:18:58AM -0500, Vijay Shankar wrote: > This patch emits instruction with proper rounding mode for nearbyint > previously > we emit xvrdpi which uses nearest away rounding mode but nearbyint requires > rounding mode to be current rounding mode > > Bootstrapped and regtested on powerpc64le-linux-gnu with no regressions.
Looks good. Hopefully it can go into the tree. > 2026-01-22 Vijay Shankar <[email protected]> > > gcc/ChangeLog: > PR target/113353 > * config/rs6000/rs6000.cc (rs6000_builtin_vectorized_function): Emit > xvrdpic > > gcc/testsuite/ChangeLog: > PR target/113353 > * gcc.target/powerpc/vsx-vector-1.c: Fix testcase > * gcc.target/powerpc/vsx-vector-2.c: Fix testcase > * gcc.target/powerpc/vsx-vector-6-func-1op.c: Fix testcase > --- > gcc/config/rs6000/rs6000.cc | 4 ++-- > gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c | 2 +- > gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c | 2 +- > gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op.c | 4 ++-- > 4 files changed, 6 insertions(+), 6 deletions(-) > > diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc > index 10b2cf983..fa0838109 100644 > --- a/gcc/config/rs6000/rs6000.cc > +++ b/gcc/config/rs6000/rs6000.cc > @@ -5696,12 +5696,12 @@ rs6000_builtin_vectorized_function (unsigned int fn, > tree type_out, > && flag_unsafe_math_optimizations > && out_mode == DFmode && out_n == 2 > && in_mode == DFmode && in_n == 2) > - return rs6000_builtin_decls[RS6000_BIF_XVRDPI]; > + return rs6000_builtin_decls[RS6000_BIF_XVRDPIC]; > if (VECTOR_UNIT_VSX_P (V4SFmode) > && flag_unsafe_math_optimizations > && out_mode == SFmode && out_n == 4 > && in_mode == SFmode && in_n == 4) > - return rs6000_builtin_decls[RS6000_BIF_XVRSPI]; > + return rs6000_builtin_decls[RS6000_BIF_XVRSPIC]; > break; > CASE_CFN_RINT: > if (VECTOR_UNIT_VSX_P (V2DFmode) > diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c > b/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c > index 4d705e46d..8b4e1bbc6 100644 > --- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c > +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c > @@ -14,7 +14,7 @@ > /* { dg-final { scan-assembler "xvrdpip" } } */ > /* { dg-final { scan-assembler "xvrdpiz" } } */ > /* { dg-final { scan-assembler "xvrdpic" } } */ > -/* { dg-final { scan-assembler "xvrdpi " } } */ > +/* { dg-final { scan-assembler "xvrdpic " } } */ > > #ifndef SIZE > #define SIZE 1024 > diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c > b/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c > index a0fe088bb..3f3d77f71 100644 > --- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c > +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c > @@ -14,7 +14,7 @@ > /* { dg-final { scan-assembler "xvrspip" } } */ > /* { dg-final { scan-assembler "xvrspiz" } } */ > /* { dg-final { scan-assembler "xvrspic" } } */ > -/* { dg-final { scan-assembler "xvrspi " } } */ > +/* { dg-final { scan-assembler "xvrspic " } } */ > > #ifndef SIZE > #define SIZE 1024 > diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op.c > b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op.c > index 6d2c64b24..7a0d42809 100644 > --- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op.c > +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op.c > @@ -10,13 +10,13 @@ > /* { dg-final { scan-assembler-times {\mxvabssp\M} 1 } } */ > /* { dg-final { scan-assembler-times {\mxvrspip\M} 1 } } */ > /* { dg-final { scan-assembler-times {\mxvrspim\M} 1 } } */ > -/* { dg-final { scan-assembler-times {\mxvrspi\M} 1 } } */ > +/* { dg-final { scan-assembler-times {\mxvrspic\M} 1 } } */ > /* { dg-final { scan-assembler-times {\mxvrspic\M} 1 } } */ > /* { dg-final { scan-assembler-times {\mxvrspiz\M} 1 } } */ > /* { dg-final { scan-assembler-times {\mxvabsdp\M} 1 } } */ > /* { dg-final { scan-assembler-times {\mxvrdpip\M} 1 } } */ > /* { dg-final { scan-assembler-times {\mxvrdpim\M} 1 } } */ > -/* { dg-final { scan-assembler-times {\mxvrdpi\M} 1 } } */ > +/* { dg-final { scan-assembler-times {\mxvrdpic\M} 1 } } */ > /* { dg-final { scan-assembler-times {\mxvrdpic\M} 1 } } */ > /* { dg-final { scan-assembler-times {\mxvrdpiz\M} 1 } } */ > /* { dg-final { scan-assembler-times {\mxvsqrtdp\M} 1 } } */ > -- > 2.47.3 > -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: [email protected]
