Before going any further, this updates the existing testcases that really
require -fno-trapping-math to now use that.
It also adds three new tests for SVE. They will however fail until the last
patch but that's fine.
Notable is testcase gcc.target/aarch64/sve/unpacked_cond_frinta_2.c which
without -ftrapping-math (which it's explicitly checking for) generates worse
code because the vectorizer forces an unneeded unpack. This is however the
same issue with how the vectorizer picks VF as we've seen a number of times.
Bootstrapped Regtested on aarch64-none-linux-gnu,
arm-none-linux-gnueabihf, x86_64-pc-linux-gnu
-m32, -m64 and no issues.
Any comments?
Thanks,
Tamar
gcc/testsuite/ChangeLog:
PR tree-optimization/122103
* gcc.target/aarch64/sve/unpacked_frinta_1.c: Add -fno-trapping-math.
* gcc.target/aarch64/sve/unpacked_frinti_1.c: Likewise.
* gcc.target/aarch64/sve/unpacked_frintm_1.c: Likewise.
* gcc.target/aarch64/sve/unpacked_frintp_1.c: Likewise.
* gcc.target/aarch64/sve/unpacked_frintx_1.c: Likewise.
* gcc.target/aarch64/sve/unpacked_frintz_1.c: Likewise.
* gcc.target/aarch64/sve/unpacked_cond_frinta_2.c: Likewise.
* gcc.target/aarch64/sve/vcond_13.c: Likewise.
* gcc.target/aarch64/sve/vcond_14.c: Likewise.
* gcc.target/aarch64/sve/vcond_15.c: Likewise.
* gcc.target/aarch64/sve/vcond_16.c: Likewise.
* gcc.target/i386/avx-pr93078.c: Likewise.
* gcc.target/i386/avx512f-pr93078.c: Likewise.
* gcc.target/aarch64/sve/pr122103_1.c: New test.
* gcc.target/aarch64/sve/pr122103_2.c: New test.
* gcc.target/aarch64/sve/pr122103_3.c: New test.
---
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr122103_1.c
b/gcc/testsuite/gcc.target/aarch64/sve/pr122103_1.c
new file mode 100644
index
0000000000000000000000000000000000000000..f06f8611393de750357de19182dad6548e972aee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr122103_1.c
@@ -0,0 +1,93 @@
+/* { dg-do run } */
+/* { dg-require-effective-target glibc } */
+/* { dg-options "-O3 -fno-math-errno -ftrapping-math -march=armv8-a+sve" } */
+
+#define _GNU_SOURCE
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <math.h>
+#include <fenv.h>
+#include <signal.h>
+
+#pragma STDC FENV_ACCESS ON
+
+__attribute__((noinline))
+void f(float *__restrict c, int *__restrict d, int n)
+{
+ for (int i = 0; i < n; i++) {
+ if (d[i] > 1000)
+ c[i] = __builtin_sqrtf(c[i]);
+ }
+}
+
+static void on_fpe(int sig)
+{
+ (void)sig;
+ puts("SIGFPE: trapped FP exception (likely FE_INVALID from sqrt on a
negative/sNaN lane)");
+ fflush(stdout);
+ __builtin_abort ();
+}
+
+int main(void)
+{
+ signal(SIGFPE, on_fpe);
+
+ // Clear flags and enable trap on invalid operations.
+ feclearexcept(FE_ALL_EXCEPT);
+ feenableexcept(FE_INVALID);
+
+ // Choose a length that is NOT a multiple of typical SVE VL (unknown at
runtime),
+ // and includes plenty of inactive lanes.
+ const int n = 37;
+
+ float *c = aligned_alloc(64, (size_t)n * sizeof(float));
+ int *d = aligned_alloc(64, (size_t)n * sizeof(int));
+ if (!c || !d) return 1;
+
+ // Construct data:
+ // - For lanes where d<=1000, put negative values in c (sqrt would be
FE_INVALID if executed).
+ // - For lanes where d>1000, put positive values in c (legal sqrt).
+ for (int i = 0; i < n; i++) {
+ if ((i % 3) == 0) {
+ d[i] = 1001; // active
+ c[i] = 4.0f; // sqrt OK
+ } else {
+ d[i] = 0; // inactive
+ c[i] = -1.0f; // sqrt would be invalid if wrongly executed
+ }
+ }
+
+ // Call f. Correct behavior: no SIGFPE, and only positions with d>1000 are
modified.
+ f(c, d, n);
+
+ // If traps are unavailable, at least report raised flags.
+ int raised = fetestexcept(FE_ALL_EXCEPT);
+ if (raised) {
+ printf("FP flags raised: 0x%x\n", raised);
+ } else {
+ puts("No FP flags raised.");
+ }
+
+ // Check results.
+ int ok = 1;
+ for (int i = 0; i < n; i++) {
+ if (d[i] > 1000) {
+ if (!(c[i] == 2.0f)) { // sqrt(4) = 2
+ printf("Mismatch at %d: expected 2.0, got %g\n", i, c[i]);
+ ok = 0;
+ }
+ } else {
+ if (!(c[i] == -1.0f)) { // must remain unchanged
+ printf("Clobber at %d: expected -1.0 unchanged, got %g\n", i,
c[i]);
+ ok = 0;
+ }
+ }
+ }
+
+ puts(ok ? "OK" : "FAIL");
+ free(c);
+ free(d);
+ return ok ? 0 : 2;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr122103_2.c
b/gcc/testsuite/gcc.target/aarch64/sve/pr122103_2.c
new file mode 100644
index
0000000000000000000000000000000000000000..a1dc080bf9e8cbb92455f7abb868fd2b98671062
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr122103_2.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -fno-math-errno -ftrapping-math -march=armv9-a" } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** f:
+** ...
+** whilelo p([0-9]+).s, wzr, w[0-9]+
+** ...
+** ld1w z0.s, p\1/z, \[x[0-9]+, x[0-9]+, lsl 2\]
+** cmpgt p\1.s, p\1/z, z[0-9]+.s, z[0-9]+.s
+** ld1w z[0-9]+.s, p\1/z, \[x[0-9]+, x[0-9]+, lsl 2\]
+** fsqrt z[0-9]+.s, p\1/m, z[0-9]+.s
+** st1w z[0-9]+.s, p\1, \[x[0-9]+, x[0-9]+, lsl 2\]
+** incw x[0-9]+
+** whilelo p\1.s, w[0-9]+, w[0-9]+
+** ...
+*/
+void f (float *__restrict c, int *__restrict d, int n)
+{
+ for (int i = 0; i < n; i++)
+ {
+ if (d[i] > 1000)
+ c[i] = __builtin_sqrtf (c[i]);
+ }
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr122103_3.c
b/gcc/testsuite/gcc.target/aarch64/sve/pr122103_3.c
new file mode 100644
index
0000000000000000000000000000000000000000..18075d7dad42d645ae58a418a7b159b7f67e108a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr122103_3.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -fno-math-errno -fno-trapping-math -march=armv9-a" } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** f:
+** ...
+** whilelo p([0-9]+).s, wzr, w[0-9]+
+** ...
+** ld1w z0.s, p\1/z, \[x[0-9]+, x[0-9]+, lsl 2\]
+** cmpgt p\1.s, p\1/z, z[0-9]+.s, z[0-9]+.s
+** ld1w z[0-9]+.s, p\1/z, \[x[0-9]+, x[0-9]+, lsl 2\]
+** fsqrt z[0-9]+.s, p[0-9]+/m, z[0-9]+.s
+** st1w z[0-9]+.s, p\1, \[x[0-9]+, x[0-9]+, lsl 2\]
+** incw x[0-9]+
+** whilelo p\1.s, w[0-9]+, w[0-9]+
+** ...
+*/
+void f (float *__restrict c, int *__restrict d, int n)
+{
+ for (int i = 0; i < n; i++)
+ {
+ if (d[i] > 1000)
+ c[i] = __builtin_sqrtf (c[i]);
+ }
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinta_2.c
b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinta_2.c
index
f20e2e6d445385a0cb71ee574229d659c92e80c7..539dffc31752ed7cfa1e27b49a43e8ea6641177c
100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinta_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinta_2.c
@@ -3,16 +3,20 @@
#include "unpacked_cond_frinta_1.c"
-/* Test that we don't drop SELs without -fno-trapping-math. */
+/* Test that operations that can raise FE exceptions are properly masked
+ even when not using -fno-trapping-math. However when using masking we hit
+ the existing problem where the vectorizer tries to match VF rather than
+ number of elements. This means we could have generated better code here
+ using widening loads, but we can't as the vectorizer forces an unrolling.
*/
-/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 2 } } */
-/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 4 } } */
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 2 { xfail *-*-* } }
} */
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 4 { xfail *-*-* } }
} */
-/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 } } */
-/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 3 } } */
-/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 3 } } */
+/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 { xfail *-*-* } }
} */
+/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 3 { xfail *-*-* } }
} */
+/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 3 { xfail *-*-* } }
} */
/* { dg-final { scan-assembler-times {\tfrinta\tz[0-9]+\.s, p[0-7]/m,
z[0-9]+\.s\n} 2 } } */
/* { dg-final { scan-assembler-times {\tfrinta\tz[0-9]+\.h, p[0-7]/m,
z[0-9]+\.h\n} 4 } } */
-/* { dg-final { scan-assembler-times {\tsel\t} 6 } } */
+/* { dg-final { scan-assembler-times {\tsel\t} 6 { xfail *-*-* } } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinta_1.c
b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinta_1.c
index
3cbdef3d99beee046048d29310c218d68f2510f9..5411089cb72dfd9cb6cbb4ac02596be73c46aa1c
100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinta_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinta_1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */
+/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize
-fno-trapping-math" } */
#include <stdint.h>
@@ -20,8 +20,8 @@ TEST_FN (__builtin_roundf16, _Float16, uint32_t, 64)
TEST_FN (__builtin_roundf32, float, uint64_t, 32)
-/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */
-/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 0 } } */
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 0 } } */
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinti_1.c
b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinti_1.c
index
7645fed5136ad4fd87274a40658243d533038aff..27401de597f6fdd5902acbe94b45f213e5860f8e
100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinti_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinti_1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */
+/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize
-fno-trapping-math" } */
#include <stdint.h>
@@ -20,8 +20,8 @@ TEST_FN (__builtin_nearbyintf16, _Float16, uint32_t, 64)
TEST_FN (__builtin_nearbyintf32, float, uint64_t, 32)
-/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */
-/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 0 } } */
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 0 } } */
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintm_1.c
b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintm_1.c
index
98f85fb5bfee5d72bc18c961e5b155f5673606a9..69502b071aa1b96129bce01795d932f1cc2961b0
100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintm_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintm_1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */
+/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize
-fno-trapping-math" } */
#include <stdint.h>
@@ -20,8 +20,8 @@ TEST_FN (__builtin_floorf16, _Float16, uint32_t, 64)
TEST_FN (__builtin_floorf32, float, uint64_t, 32)
-/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */
-/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 0 } } */
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 0 } } */
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintp_1.c
b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintp_1.c
index
f2336979ad0f6c134038aa20fa0711ebb49c442f..12a7c7eadfce44671e84002a7ac32802225e8e79
100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintp_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintp_1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */
+/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize
-fno-trapping-math" } */
#include <stdint.h>
@@ -20,8 +20,8 @@ TEST_FN (__builtin_ceilf16, _Float16, uint32_t, 64)
TEST_FN (__builtin_ceilf32, float, uint64_t, 32)
-/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */
-/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 0 } } */
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 0 } } */
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintx_1.c
b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintx_1.c
index
73403a54ecbba685ae8e8d89ca5328f3d6403832..152bda5cc2bab8e31d00a0b39ee4c6bae040891d
100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintx_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintx_1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */
+/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize
-fno-trapping-math" } */
#include <stdint.h>
@@ -20,8 +20,8 @@ TEST_FN (__builtin_rintf16, _Float16, uint32_t, 64)
TEST_FN (__builtin_rintf32, float, uint64_t, 32)
-/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */
-/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 0 } } */
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 0 } } */
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintz_1.c
b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintz_1.c
index
73778431c2ee33fc4444ff3b231ba3275be8172a..f09f19cbc5f267611c06021f3a78e40c23f72691
100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintz_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintz_1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */
+/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize
-fno-trapping-math" } */
#include <stdint.h>
@@ -20,8 +20,8 @@ TEST_FN (__builtin_truncf16, _Float16, uint32_t, 64)
TEST_FN (__builtin_truncf32, float, uint64_t, 32)
-/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */
-/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 0 } } */
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 0 } } */
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_13.c
b/gcc/testsuite/gcc.target/aarch64/sve/vcond_13.c
index
3c3aa00f6741344e936768067431b0c27efae81c..701991946cb87b37fe7e250154f034e365e32245
100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/vcond_13.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/vcond_13.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */
#define N 119
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_14.c
b/gcc/testsuite/gcc.target/aarch64/sve/vcond_14.c
index
1144461dec0ee739025fd31c7904b121da170c75..a5aa85356c68b917a45cdb5c31c192bf1ac836ed
100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/vcond_14.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/vcond_14.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */
#define N 119
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_15.c
b/gcc/testsuite/gcc.target/aarch64/sve/vcond_15.c
index
4967074072c7197a288db3505a83ddf3378a4f9d..f8c5f305832031a36f0f414c054cf7c63ed385c1
100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/vcond_15.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/vcond_15.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */
#define N 119
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_16.c
b/gcc/testsuite/gcc.target/aarch64/sve/vcond_16.c
index
7fa98716830bd576d10a6f7e7a0fd83147bf7808..115c9903511c6714173a9198e96605dde607bbf3
100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/vcond_16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/vcond_16.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */
#define N 119
diff --git a/gcc/testsuite/gcc.target/i386/avx-pr93078.c
b/gcc/testsuite/gcc.target/i386/avx-pr93078.c
index
3fedeaa0c656e98f59374c9a12af76d4f98c5b75..e4834918e099c52ad5b5e59a3a1c38b517accd39
100644
--- a/gcc/testsuite/gcc.target/i386/avx-pr93078.c
+++ b/gcc/testsuite/gcc.target/i386/avx-pr93078.c
@@ -1,6 +1,6 @@
/* PR target/93078 */
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize -mavx -mno-avx2
-mprefer-vector-width=256 -masm=att" } */
+/* { dg-options "-O2 -ftree-vectorize -mavx -mno-avx2
-mprefer-vector-width=256 -masm=att -fno-trapping-math" } */
/* { dg-final { scan-assembler "vroundps\[ \t]\+\\\$12,\[^\n\r]*%y" } } */
/* { dg-final { scan-assembler "vroundps\[ \t]\+\\\$4,\[^\n\r]*%y" } } */
/* { dg-final { scan-assembler "vroundpd\[ \t]\+\\\$12,\[^\n\r]*%y" } } */
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-pr93078.c
b/gcc/testsuite/gcc.target/i386/avx512f-pr93078.c
index
72d6c25bff14ac383903258a9e5a3eb8eb8a5df0..b9e308932d9592f1578aa3318582ef9de181f56f
100644
--- a/gcc/testsuite/gcc.target/i386/avx512f-pr93078.c
+++ b/gcc/testsuite/gcc.target/i386/avx512f-pr93078.c
@@ -1,6 +1,6 @@
/* PR target/93078 */
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize -mavx512f -mprefer-vector-width=512
-masm=att" } */
+/* { dg-options "-O2 -ftree-vectorize -mavx512f -mprefer-vector-width=512
-masm=att -fno-trapping-math" } */
/* { dg-final { scan-assembler "vrndscaleps\[ \t]\+\\\$12,\[^\n\r]*%z" } } */
/* { dg-final { scan-assembler "vrndscaleps\[ \t]\+\\\$4,\[^\n\r]*%z" } } */
/* { dg-final { scan-assembler "vrndscalepd\[ \t]\+\\\$12,\[^\n\r]*%z" } } */
--
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr122103_1.c b/gcc/testsuite/gcc.target/aarch64/sve/pr122103_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..f06f8611393de750357de19182dad6548e972aee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr122103_1.c
@@ -0,0 +1,93 @@
+/* { dg-do run } */
+/* { dg-require-effective-target glibc } */
+/* { dg-options "-O3 -fno-math-errno -ftrapping-math -march=armv8-a+sve" } */
+
+#define _GNU_SOURCE
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <math.h>
+#include <fenv.h>
+#include <signal.h>
+
+#pragma STDC FENV_ACCESS ON
+
+__attribute__((noinline))
+void f(float *__restrict c, int *__restrict d, int n)
+{
+ for (int i = 0; i < n; i++) {
+ if (d[i] > 1000)
+ c[i] = __builtin_sqrtf(c[i]);
+ }
+}
+
+static void on_fpe(int sig)
+{
+ (void)sig;
+ puts("SIGFPE: trapped FP exception (likely FE_INVALID from sqrt on a negative/sNaN lane)");
+ fflush(stdout);
+ __builtin_abort ();
+}
+
+int main(void)
+{
+ signal(SIGFPE, on_fpe);
+
+ // Clear flags and enable trap on invalid operations.
+ feclearexcept(FE_ALL_EXCEPT);
+ feenableexcept(FE_INVALID);
+
+ // Choose a length that is NOT a multiple of typical SVE VL (unknown at runtime),
+ // and includes plenty of inactive lanes.
+ const int n = 37;
+
+ float *c = aligned_alloc(64, (size_t)n * sizeof(float));
+ int *d = aligned_alloc(64, (size_t)n * sizeof(int));
+ if (!c || !d) return 1;
+
+ // Construct data:
+ // - For lanes where d<=1000, put negative values in c (sqrt would be FE_INVALID if executed).
+ // - For lanes where d>1000, put positive values in c (legal sqrt).
+ for (int i = 0; i < n; i++) {
+ if ((i % 3) == 0) {
+ d[i] = 1001; // active
+ c[i] = 4.0f; // sqrt OK
+ } else {
+ d[i] = 0; // inactive
+ c[i] = -1.0f; // sqrt would be invalid if wrongly executed
+ }
+ }
+
+ // Call f. Correct behavior: no SIGFPE, and only positions with d>1000 are modified.
+ f(c, d, n);
+
+ // If traps are unavailable, at least report raised flags.
+ int raised = fetestexcept(FE_ALL_EXCEPT);
+ if (raised) {
+ printf("FP flags raised: 0x%x\n", raised);
+ } else {
+ puts("No FP flags raised.");
+ }
+
+ // Check results.
+ int ok = 1;
+ for (int i = 0; i < n; i++) {
+ if (d[i] > 1000) {
+ if (!(c[i] == 2.0f)) { // sqrt(4) = 2
+ printf("Mismatch at %d: expected 2.0, got %g\n", i, c[i]);
+ ok = 0;
+ }
+ } else {
+ if (!(c[i] == -1.0f)) { // must remain unchanged
+ printf("Clobber at %d: expected -1.0 unchanged, got %g\n", i, c[i]);
+ ok = 0;
+ }
+ }
+ }
+
+ puts(ok ? "OK" : "FAIL");
+ free(c);
+ free(d);
+ return ok ? 0 : 2;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr122103_2.c b/gcc/testsuite/gcc.target/aarch64/sve/pr122103_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..a1dc080bf9e8cbb92455f7abb868fd2b98671062
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr122103_2.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -fno-math-errno -ftrapping-math -march=armv9-a" } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** f:
+** ...
+** whilelo p([0-9]+).s, wzr, w[0-9]+
+** ...
+** ld1w z0.s, p\1/z, \[x[0-9]+, x[0-9]+, lsl 2\]
+** cmpgt p\1.s, p\1/z, z[0-9]+.s, z[0-9]+.s
+** ld1w z[0-9]+.s, p\1/z, \[x[0-9]+, x[0-9]+, lsl 2\]
+** fsqrt z[0-9]+.s, p\1/m, z[0-9]+.s
+** st1w z[0-9]+.s, p\1, \[x[0-9]+, x[0-9]+, lsl 2\]
+** incw x[0-9]+
+** whilelo p\1.s, w[0-9]+, w[0-9]+
+** ...
+*/
+void f (float *__restrict c, int *__restrict d, int n)
+{
+ for (int i = 0; i < n; i++)
+ {
+ if (d[i] > 1000)
+ c[i] = __builtin_sqrtf (c[i]);
+ }
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr122103_3.c b/gcc/testsuite/gcc.target/aarch64/sve/pr122103_3.c
new file mode 100644
index 0000000000000000000000000000000000000000..18075d7dad42d645ae58a418a7b159b7f67e108a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr122103_3.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -fno-math-errno -fno-trapping-math -march=armv9-a" } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** f:
+** ...
+** whilelo p([0-9]+).s, wzr, w[0-9]+
+** ...
+** ld1w z0.s, p\1/z, \[x[0-9]+, x[0-9]+, lsl 2\]
+** cmpgt p\1.s, p\1/z, z[0-9]+.s, z[0-9]+.s
+** ld1w z[0-9]+.s, p\1/z, \[x[0-9]+, x[0-9]+, lsl 2\]
+** fsqrt z[0-9]+.s, p[0-9]+/m, z[0-9]+.s
+** st1w z[0-9]+.s, p\1, \[x[0-9]+, x[0-9]+, lsl 2\]
+** incw x[0-9]+
+** whilelo p\1.s, w[0-9]+, w[0-9]+
+** ...
+*/
+void f (float *__restrict c, int *__restrict d, int n)
+{
+ for (int i = 0; i < n; i++)
+ {
+ if (d[i] > 1000)
+ c[i] = __builtin_sqrtf (c[i]);
+ }
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinta_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinta_2.c
index f20e2e6d445385a0cb71ee574229d659c92e80c7..539dffc31752ed7cfa1e27b49a43e8ea6641177c 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinta_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinta_2.c
@@ -3,16 +3,20 @@
#include "unpacked_cond_frinta_1.c"
-/* Test that we don't drop SELs without -fno-trapping-math. */
+/* Test that operations that can raise FE exceptions are properly masked
+ even when not using -fno-trapping-math. However when using masking we hit
+ the existing problem where the vectorizer tries to match VF rather than
+ number of elements. This means we could have generated better code here
+ using widening loads, but we can't as the vectorizer forces an unrolling. */
-/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 2 } } */
-/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 4 } } */
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 2 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 4 { xfail *-*-* } } } */
-/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 } } */
-/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 3 } } */
-/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 3 } } */
+/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 3 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 3 { xfail *-*-* } } } */
/* { dg-final { scan-assembler-times {\tfrinta\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 2 } } */
/* { dg-final { scan-assembler-times {\tfrinta\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 4 } } */
-/* { dg-final { scan-assembler-times {\tsel\t} 6 } } */
+/* { dg-final { scan-assembler-times {\tsel\t} 6 { xfail *-*-* } } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinta_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinta_1.c
index 3cbdef3d99beee046048d29310c218d68f2510f9..5411089cb72dfd9cb6cbb4ac02596be73c46aa1c 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinta_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinta_1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */
+/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */
#include <stdint.h>
@@ -20,8 +20,8 @@ TEST_FN (__builtin_roundf16, _Float16, uint32_t, 64)
TEST_FN (__builtin_roundf32, float, uint64_t, 32)
-/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */
-/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 0 } } */
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 0 } } */
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinti_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinti_1.c
index 7645fed5136ad4fd87274a40658243d533038aff..27401de597f6fdd5902acbe94b45f213e5860f8e 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinti_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinti_1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */
+/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */
#include <stdint.h>
@@ -20,8 +20,8 @@ TEST_FN (__builtin_nearbyintf16, _Float16, uint32_t, 64)
TEST_FN (__builtin_nearbyintf32, float, uint64_t, 32)
-/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */
-/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 0 } } */
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 0 } } */
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintm_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintm_1.c
index 98f85fb5bfee5d72bc18c961e5b155f5673606a9..69502b071aa1b96129bce01795d932f1cc2961b0 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintm_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintm_1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */
+/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */
#include <stdint.h>
@@ -20,8 +20,8 @@ TEST_FN (__builtin_floorf16, _Float16, uint32_t, 64)
TEST_FN (__builtin_floorf32, float, uint64_t, 32)
-/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */
-/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 0 } } */
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 0 } } */
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintp_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintp_1.c
index f2336979ad0f6c134038aa20fa0711ebb49c442f..12a7c7eadfce44671e84002a7ac32802225e8e79 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintp_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintp_1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */
+/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */
#include <stdint.h>
@@ -20,8 +20,8 @@ TEST_FN (__builtin_ceilf16, _Float16, uint32_t, 64)
TEST_FN (__builtin_ceilf32, float, uint64_t, 32)
-/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */
-/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 0 } } */
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 0 } } */
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintx_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintx_1.c
index 73403a54ecbba685ae8e8d89ca5328f3d6403832..152bda5cc2bab8e31d00a0b39ee4c6bae040891d 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintx_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintx_1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */
+/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */
#include <stdint.h>
@@ -20,8 +20,8 @@ TEST_FN (__builtin_rintf16, _Float16, uint32_t, 64)
TEST_FN (__builtin_rintf32, float, uint64_t, 32)
-/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */
-/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 0 } } */
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 0 } } */
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintz_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintz_1.c
index 73778431c2ee33fc4444ff3b231ba3275be8172a..f09f19cbc5f267611c06021f3a78e40c23f72691 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintz_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintz_1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */
+/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */
#include <stdint.h>
@@ -20,8 +20,8 @@ TEST_FN (__builtin_truncf16, _Float16, uint32_t, 64)
TEST_FN (__builtin_truncf32, float, uint64_t, 32)
-/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */
-/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 0 } } */
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 0 } } */
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_13.c b/gcc/testsuite/gcc.target/aarch64/sve/vcond_13.c
index 3c3aa00f6741344e936768067431b0c27efae81c..701991946cb87b37fe7e250154f034e365e32245 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/vcond_13.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/vcond_13.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */
#define N 119
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_14.c b/gcc/testsuite/gcc.target/aarch64/sve/vcond_14.c
index 1144461dec0ee739025fd31c7904b121da170c75..a5aa85356c68b917a45cdb5c31c192bf1ac836ed 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/vcond_14.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/vcond_14.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */
#define N 119
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_15.c b/gcc/testsuite/gcc.target/aarch64/sve/vcond_15.c
index 4967074072c7197a288db3505a83ddf3378a4f9d..f8c5f305832031a36f0f414c054cf7c63ed385c1 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/vcond_15.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/vcond_15.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */
#define N 119
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_16.c b/gcc/testsuite/gcc.target/aarch64/sve/vcond_16.c
index 7fa98716830bd576d10a6f7e7a0fd83147bf7808..115c9903511c6714173a9198e96605dde607bbf3 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/vcond_16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/vcond_16.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */
#define N 119
diff --git a/gcc/testsuite/gcc.target/i386/avx-pr93078.c b/gcc/testsuite/gcc.target/i386/avx-pr93078.c
index 3fedeaa0c656e98f59374c9a12af76d4f98c5b75..e4834918e099c52ad5b5e59a3a1c38b517accd39 100644
--- a/gcc/testsuite/gcc.target/i386/avx-pr93078.c
+++ b/gcc/testsuite/gcc.target/i386/avx-pr93078.c
@@ -1,6 +1,6 @@
/* PR target/93078 */
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize -mavx -mno-avx2 -mprefer-vector-width=256 -masm=att" } */
+/* { dg-options "-O2 -ftree-vectorize -mavx -mno-avx2 -mprefer-vector-width=256 -masm=att -fno-trapping-math" } */
/* { dg-final { scan-assembler "vroundps\[ \t]\+\\\$12,\[^\n\r]*%y" } } */
/* { dg-final { scan-assembler "vroundps\[ \t]\+\\\$4,\[^\n\r]*%y" } } */
/* { dg-final { scan-assembler "vroundpd\[ \t]\+\\\$12,\[^\n\r]*%y" } } */
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-pr93078.c b/gcc/testsuite/gcc.target/i386/avx512f-pr93078.c
index 72d6c25bff14ac383903258a9e5a3eb8eb8a5df0..b9e308932d9592f1578aa3318582ef9de181f56f 100644
--- a/gcc/testsuite/gcc.target/i386/avx512f-pr93078.c
+++ b/gcc/testsuite/gcc.target/i386/avx512f-pr93078.c
@@ -1,6 +1,6 @@
/* PR target/93078 */
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize -mavx512f -mprefer-vector-width=512 -masm=att" } */
+/* { dg-options "-O2 -ftree-vectorize -mavx512f -mprefer-vector-width=512 -masm=att -fno-trapping-math" } */
/* { dg-final { scan-assembler "vrndscaleps\[ \t]\+\\\$12,\[^\n\r]*%z" } } */
/* { dg-final { scan-assembler "vrndscaleps\[ \t]\+\\\$4,\[^\n\r]*%z" } } */
/* { dg-final { scan-assembler "vrndscalepd\[ \t]\+\\\$12,\[^\n\r]*%z" } } */
