Some backends, RISC-V included, wrap shift counts in subreg which
current cond zero arith wasn't handling.
This came up up when looking at the original submission of cond zero
arith which did handle subregs but then was omitted to for initial
simplicity and then got lost along the way.
gcc/ChangeLog:
* ifcvt.cc (get_base_reg): Handle subreg.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zicond_ifcvt_opt.c: Adjust increased czero counts.
Signed-off-by: Vineet Gupta <[email protected]>
---
gcc/ifcvt.cc | 2 ++
gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc
index 280f398cee6c..802c5e99afcb 100644
--- a/gcc/ifcvt.cc
+++ b/gcc/ifcvt.cc
@@ -3112,6 +3112,8 @@ get_base_reg (rtx exp)
{
if (REG_P (exp))
return exp;
+ else if (SUBREG_P (exp))
+ return SUBREG_REG (exp);
return NULL_RTX;
}
diff --git a/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c
b/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c
index a02a2757d2cf..d5310690539c 100644
--- a/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c
+++ b/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c
@@ -774,5 +774,5 @@ test_AND_eqz_x_2_reverse_bin_oprands (long x, long z, long
c)
x = z & x;
return x;
}
-/* { dg-final { scan-assembler-times {czero\.eqz} 36 } } */
+/* { dg-final { scan-assembler-times {czero\.eqz} 41 } } */
/* { dg-final { scan-assembler-times {czero\.nez} 36 } } */
--
2.43.0
