> Could you provide testcase to verified select_vl begin generated for VLS mode? > I can't found testcase, I tried param-autovec-mode.c > and select_vl-2.c (with --param=riscv-autovec-mode=V4QI) > and both cases are generated MIN_EXPR rather than SELECT_VL.
Really? I thought it would trigger in param-autovec-mode but haven't verified the code-gen. I mean it's not terribly common, just for VLS epilogue loops. But yes, I'll add a more specific test. > ^^^ I think we should not assert TARGET_ZBB here, although I that's > because we try to expand UMIN > >> + rtx nunits_reg = gen_reg_rtx (Pmode); >> + emit_move_insn (nunits_reg, GEN_INT (nunits.to_constant ())); >> + rtx avl_adj = gen_reg_rtx (Pmode); >> + emit_move_insn (avl_adj, simplify_gen_binary >> + (UMIN, Pmode, ops[1], nunits_reg)); > > Maybe expand_simple_binop rather than simplify_gen_binary here to > avoid we require ZBB I refrained from doing so on purpose because the umin codegen is very verbose and would drown a lot of the vectorization benefit for small loops. I'd much rather have the non-len VLS flow when Zbb is unavailable. -- Regards Robin
