I found the only user for mode_idx is get_insn_vtype_mode, and the change seems not really satisfy the semantic for that `function name`.
However...the user of get_insn_vtype_mode is imm_avl_p and few other functions in following logic, what we really care about is SEW/LMUL ratio here rather than the exact mode here, so it will work correctly even we don't the satisfy the semantic of get_insn_vtype_mode... So LGTM, and I agree we should spend a little more time to clean that up later...maybe GCC 17... On Tue, Dec 9, 2025 at 3:58 AM Robin Dapp <[email protected]> wrote: > > Hi, > > Similar to 116149 we use the mode size of operand MODE_IDX but that > one could refer to a broadcast scalar. Use operand 3 for potential > scalar patterns instead. I hope to have caught every possible offender. > > I'm not happy with the mode_idx/mode attribute/... situation. Mode and > mode_idx in particular appear interchangeable but aren't and are used for > different things. Long-term we really need a better way of dealing with > both. > > Another note: pr123022.c appears unsupported on the server I tested it > despite qemu VLEN=512, while it is supported and passes on my laptop, > also with qemu VLEN=512. Sigh. > > Regtested on rv64gcv_zvl512b. > > Regards > Robin > > PR target/123022 > > gcc/ChangeLog: > > * config/riscv/vector.md: Add mode_idx attribute. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/pr123022-2.c: New test. > * gcc.target/riscv/rvv/autovec/pr123022.c: New test. > --- > gcc/config/riscv/vector.md | 8 ++++++++ > .../gcc.target/riscv/rvv/autovec/pr123022-2.c | 6 ++++++ > .../gcc.target/riscv/rvv/autovec/pr123022.c | 20 +++++++++++++++++++ > 3 files changed, 34 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123022-2.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123022.c > > diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md > index 4130f8776b8..53083eb5018 100644 > --- a/gcc/config/riscv/vector.md > +++ b/gcc/config/riscv/vector.md > @@ -4199,6 +4199,7 @@ (define_insn > "@pred_single_widen_<plus_minus:optab><any_extend:su><mode>_scalar" > "TARGET_VECTOR" > "vw<plus_minus:insn><any_extend:u>.wx\t%0,%3,%z4%p1" > [(set_attr "type" "vi<widen_binop_insn_type>") > + (set_attr "mode_idx" "3") > (set_attr "mode" "<V_DOUBLE_TRUNC>")]) > > (define_insn "@pred_single_widen_add<any_extend:su><mode>_extended_scalar" > @@ -4465,6 +4466,7 @@ (define_insn "@pred_<optab><mode>_scalar" > "TARGET_VECTOR" > "v<insn>.vx\t%0,%3,%4%p1" > [(set_attr "type" "<int_binop_insn_type>") > + (set_attr "mode_idx" "3") > (set_attr "mode" "<MODE>")]) > > (define_insn "@pred_<optab><mode>_scalar" > @@ -4486,6 +4488,7 @@ (define_insn "@pred_<optab><mode>_scalar" > "TARGET_VECTOR" > "v<insn>.vx\t%0,%3,%4%p1" > [(set_attr "type" "<int_binop_insn_type>") > + (set_attr "mode_idx" "3") > (set_attr "mode" "<MODE>")]) > > (define_expand "@pred_<optab><mode>_scalar" > @@ -4540,6 +4543,7 @@ (define_insn "*pred_<optab><mode>_scalar" > "TARGET_VECTOR" > "v<insn>.vx\t%0,%3,%4%p1" > [(set_attr "type" "<int_binop_insn_type>") > + (set_attr "mode_idx" "3") > (set_attr "mode" "<MODE>")]) > > (define_insn "*pred_<optab><mode>_extended_scalar" > @@ -4562,6 +4566,7 @@ (define_insn "*pred_<optab><mode>_extended_scalar" > "TARGET_VECTOR && !TARGET_64BIT" > "v<insn>.vx\t%0,%3,%4%p1" > [(set_attr "type" "<int_binop_insn_type>") > + (set_attr "mode_idx" "3") > (set_attr "mode" "<MODE>")]) > > (define_expand "@pred_<optab><mode>_scalar" > @@ -4616,6 +4621,7 @@ (define_insn "*pred_<optab><mode>_scalar" > "TARGET_VECTOR" > "v<insn>.vx\t%0,%3,%z4%p1" > [(set_attr "type" "<int_binop_insn_type>") > + (set_attr "mode_idx" "3") > (set_attr "mode" "<MODE>")]) > > (define_insn "*pred_<optab><mode>_extended_scalar" > @@ -4638,6 +4644,7 @@ (define_insn "*pred_<optab><mode>_extended_scalar" > "TARGET_VECTOR && !TARGET_64BIT" > "v<insn>.vx\t%0,%3,%z4%p1" > [(set_attr "type" "<int_binop_insn_type>") > + (set_attr "mode_idx" "3") > (set_attr "mode" "<MODE>")]) > > (define_insn "@pred_<sat_op><mode>" > @@ -4683,6 +4690,7 @@ (define_insn "@pred_<sat_op><mode>_scalar" > "TARGET_VECTOR" > "v<sat_op>.vx\t%0,%3,%z4%p1" > [(set_attr "type" "<sat_insn_type>") > + (set_attr "mode_idx" "3") > (set_attr "mode" "<MODE>")]) > > (define_insn "@pred_<sat_op><mode>_scalar" > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123022-2.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123022-2.c > new file mode 100644 > index 00000000000..0562b566fa8 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123022-2.c > @@ -0,0 +1,6 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O3 -march=rv64gcv_zvl512b -mabi=lp64d > -mrvv-vector-bits=zvl -fsigned-char" } */ > + > +#include "pr123022.c" > + > +/* { dg-final { scan-assembler-not "vset.*zero,1," } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123022.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123022.c > new file mode 100644 > index 00000000000..cf80d5d7882 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123022.c > @@ -0,0 +1,20 @@ > +/* { dg-do run { target rvv_zvl512b_ok } } */ > +/* { dg-options "-O3 -march=rv64gcv_zvl512b -mabi=lp64d > -mrvv-vector-bits=zvl -fsigned-char" } */ > +unsigned e[2][2]; > +long a; > +char c[2]; > + > +int > +main () > +{ > + long long b; > + c[1] = 3; > + for (unsigned h = 0; h < 2; h++) > + for (int i = c[0]; i < 5; i += 5) > + for (int j = 0; j < 219; j++) > + a = c[h] ? e[h][h] + 3326195747 : 0; > + > + b = a; > + if (b != 3326195747) > + __builtin_abort (); > +} > -- > 2.51.1 >
